From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 236A82194D395 for ; Tue, 2 May 2017 10:03:53 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 May 2017 10:03:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,280,1491289200"; d="scan'208";a="963536089" Received: from orsmsx103.amr.corp.intel.com ([10.22.225.130]) by orsmga003.jf.intel.com with ESMTP; 02 May 2017 10:03:48 -0700 Received: from orsmsx158.amr.corp.intel.com (10.22.240.20) by ORSMSX103.amr.corp.intel.com (10.22.225.130) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 2 May 2017 10:03:48 -0700 Received: from orsmsx113.amr.corp.intel.com ([169.254.9.59]) by ORSMSX158.amr.corp.intel.com ([169.254.10.159]) with mapi id 14.03.0319.002; Tue, 2 May 2017 10:03:46 -0700 From: "Kinney, Michael D" To: Andrew Fish , Amit kumar , "Kinney, Michael D" CC: "edk2-devel@lists.01.org" Thread-Topic: [edk2] Accessing AVX/AVX2 instruction in UEFI. Thread-Index: AQHSw1aHlzHac7B0QUKzG1nNlbXHNqHhPsdw Date: Tue, 2 May 2017 17:03:45 +0000 Message-ID: References: <0E40AA0F-3FDD-420D-9982-43FB8E0DE81A@apple.com> In-Reply-To: <0E40AA0F-3FDD-420D-9982-43FB8E0DE81A@apple.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_IC x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYjg2YTBjNjYtZjkwZi00MDk1LWE0ZmUtMWIxYzAxMGU2MGM1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Ilo0bVVJMGhQTDQ3NENJREZxYjYrOFowdmVcL3J6ZXdpZUtmUll1anNcL3VrYz0ifQ== dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Subject: Re: Accessing AVX/AVX2 instruction in UEFI. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 May 2017 17:03:53 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Amit, The information from Andrew is correct. The document that covers this topic is the=20 Intel(r) 64 and IA-32 Architectures Software Developer Manuals https://software.intel.com/en-us/articles/intel-sdm Volume 1, Section 13.5.3 describes the AVX State. There are=20 More details about detecting and enabling different AVX features in that document. If the CPU supports AVX, then the basic assembly instructions required to use AVX instructions are the following that sets bits 0, 1, 2 of XCR0. mov rcx, 0 xgetbv or rax, 0007h xsetbv One additional item you need to be aware of is that UEFI firmware only saves/Restores CPU registers required for the UEFI ABI calling convention when a timer interrupt or exception is processed. This means CPU state such as the YMM registers are not saved/restored across an interrupt and may be modified if code in interrupt context also uses YMM registers. When you enable the use of extended registers, interrupts should be=20 saved/disabled and restored around the extended register usage. You can use the following functions from MdePkg BaseLib to do this /** Disables CPU interrupts and returns the interrupt state prior to the disa= ble operation. @retval TRUE CPU interrupts were enabled on entry to this call. @retval FALSE CPU interrupts were disabled on entry to this call. **/ BOOLEAN EFIAPI SaveAndDisableInterrupts ( VOID ); /** Set the current CPU interrupt state. Sets the current CPU interrupt state to the state specified by InterruptState. If InterruptState is TRUE, then interrupts are enabled. I= f InterruptState is FALSE, then interrupts are disabled. InterruptState is returned. @param InterruptState TRUE if interrupts should enabled. FALSE if interrupts should be disabled. @return InterruptState **/ BOOLEAN EFIAPI SetInterruptState ( IN BOOLEAN InterruptState ); Algorithm: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D { BOOLEAN InterruptState; InterruptState =3D SaveAndDisableInterrupts(); // Enable use of AVX/AVX2 instructions // Use AVX/AVX2 instructions SetInterruptState (InterruptState); } Best regards, Mike > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of An= drew Fish > Sent: Tuesday, May 2, 2017 8:12 AM > To: Amit kumar > Cc: edk2-devel@lists.01.org > Subject: Re: [edk2] Accessing AVX/AVX2 instruction in UEFI. >=20 >=20 > > On May 2, 2017, at 6:57 AM, Amit kumar wrote: > > > > Hi, > > > > Am trying to optimize an application using AVX/AVX2, but my code hangs = while trying > to access YMM registers. > > The instruction where my code hangs is : > > > > > > vmovups ymm0, YMMWORD PTR [rax] > > > > > > I have verified the cpuid in OS and it supports AVX and AVX2 instructio= n. Processor > i7 6th gen. > > Can somebody help me out here ? Is there a way to enable YMM registers = ? > > >=20 > Amit, >=20 > I think these instructions will generate an illegal instruction fault unt= il you enable > AVX. You need to check the Cpu ID bits in your code, then write BIT18 of = CR4. After > that XGETBV/XSETBV instructions are enabled and you can or in the lower 2= bits of > XCR0. This basic operation is in the Intel Docs, it is just hard to find.= Usually the > OS has done this for the programmer and all the code needs to do is check= the CPU ID. >=20 > Thanks, >=20 > Andrew Fish >=20 > > > > Thanks And Regards > > Amit Kumar > > > > _______________________________________________ > > edk2-devel mailing list > > edk2-devel@lists.01.org > > https://lists.01.org/mailman/listinfo/edk2-devel >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel