From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 31E1B21A02F2D for ; Mon, 22 May 2017 08:13:28 -0700 (PDT) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 May 2017 08:13:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,377,1491289200"; d="scan'208";a="103966162" Received: from orsmsx102.amr.corp.intel.com ([10.22.225.129]) by orsmga005.jf.intel.com with ESMTP; 22 May 2017 08:13:27 -0700 Received: from orsmsx151.amr.corp.intel.com (10.22.226.38) by ORSMSX102.amr.corp.intel.com (10.22.225.129) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 22 May 2017 08:13:26 -0700 Received: from orsmsx113.amr.corp.intel.com ([169.254.9.59]) by ORSMSX151.amr.corp.intel.com ([169.254.7.57]) with mapi id 14.03.0319.002; Mon, 22 May 2017 08:13:26 -0700 From: "Kinney, Michael D" To: "Fan, Jeff" , "edk2-devel@lists.01.org" , "Kinney, Michael D" CC: Andrew Fish Thread-Topic: [Patch] UefiCpuPkg/MpInitLib: Fix X64 XCODE5/NASM compatibility issues Thread-Index: AQHS0mUhinNhImd6nka0oyIwI1kLZ6IAImKAgABUTSA= Date: Mon, 22 May 2017 15:13:26 +0000 Message-ID: References: <1495393490-16884-1-git-send-email-michael.d.kinney@intel.com> <542CF652F8836A4AB8DBFAAD40ED192A4C5E7059@shsmsx102.ccr.corp.intel.com> In-Reply-To: <542CF652F8836A4AB8DBFAAD40ED192A4C5E7059@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_IC x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTc1NzcxNzEtMGE1Mi00YWZiLWE4NmMtMmQzMTNjYjgyYTA0IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Ik9POUk1Rmo0WCtWeUhkT3lXMis5dFBJbW9OSnhnZFZqcEYrZ2VVWWJnN009In0= dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Subject: Re: [Patch] UefiCpuPkg/MpInitLib: Fix X64 XCODE5/NASM compatibility issues X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 22 May 2017 15:13:28 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Jeff, I agree. I thought of a 2nd method to pass the address through the=20 structure that is shared between the C and assembly code. I will work on a 2nd version of the patch that is both XIP and PIE compatible. Mike > -----Original Message----- > From: Fan, Jeff > Sent: Sunday, May 21, 2017 8:10 PM > To: Kinney, Michael D ; edk2-devel@lists.01.o= rg > Cc: Andrew Fish > Subject: RE: [Patch] UefiCpuPkg/MpInitLib: Fix X64 XCODE5/NASM compatibil= ity issues >=20 > Mike, >=20 > This piece of code will be shared for CPU PEI/DXE MP driver. If PEI is 64= bit, this > piece of code maybe located on FLASH. >=20 > We cannot change the value in InitialzeFloatingPointUnitsAddress if the c= ode located > on FALSH in AsmGetAddressMap(). >=20 > We need to update the InitialzeFloatingPointUnitsAddress after this piece= of code > copied into AP reset vector in memory > in BackupAndPrepareWakeupBuffer(). >=20 > Thanks! > Jeff >=20 > -----Original Message----- > From: Kinney, Michael D > Sent: Monday, May 22, 2017 3:05 AM > To: edk2-devel@lists.01.org > Cc: Andrew Fish; Fan, Jeff; Kinney, Michael D > Subject: [Patch] UefiCpuPkg/MpInitLib: Fix X64 XCODE5/NASM compatibility = issues >=20 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D565 >=20 > Fix NASM compatibility issues with XCODE5 tool chain. > The XCODE5 tool chain for X64 builds using PIE (Position Independent Exec= utable). For > most assembly sources using PIE mode does not cause any issues. >=20 > However, if assembly code is copied to a different address (such as AP st= artup code in > the MpInitLib), then the > X64 assembly source must be implemented to be compatible with PIE mode th= at uses RIP > relative addressing. >=20 > The specific changes in this patch are: >=20 > * Use LEA instruction instead of MOV instruction to lookup > the addresses of functions. >=20 > * The assembly function RendezvousFunnelProc() is copied > below 1MB so it can be executed as part of the MpInitLib > AP startup sequence. RendezvousFunnelProc() calls the > external function InitializeFloatingPointUnits(). The > absolute address of InitializeFloatingPointUnits() must > resolved and saved to a data element that is part of > RendezvousFunnelProc() before RendezvousFunnelProc() is > copied below 1MB. This work is done in AsmGetAddressMap(). >=20 > Cc: Andrew Fish > Cc: Jeff Fan > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Michael D Kinney > --- > UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 20 ++++++++++++++++---- > 1 file changed, 16 insertions(+), 4 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > index fa54d01..c943a09 100644 > --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > @@ -1,5 +1,5 @@ > ;-----------------------------------------------------------------------= ------- ; -; > Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
> +; Copyright (c) 2015 - 2017, Intel Corporation. All rights > +reserved.
> ; This program and the accompanying materials ; are licensed and made a= vailable > under the terms and conditions of the BSD License ; which accompanies th= is > distribution. The full text of the license may be found at @@ -201,7 +20= 1,8 @@ > CProcedureInvoke: > push rbp > mov rbp, rsp >=20 > - mov rax, ASM_PFX(InitializeFloatingPointUnits) > + lea rax, [InitialzeFloatingPointUnitsAddress] > + mov rax, qword [rax] > sub rsp, 20h > call rax ; Call assembly function to initialize = FPU per UEFI > spec > add rsp, 20h > @@ -219,6 +220,10 @@ CProcedureInvoke: > add rsp, 20h > jmp $ ; Should never reach here >=20 > +InitialzeFloatingPointUnitsAddress: > + DQ 0 ; Provide storage for absolute adddress= of > + ; the InitializeFloatingPointUnits() > +function > + > RendezvousFunnelProcEnd: >=20 > ;-----------------------------------------------------------------------= ------------- > - > @@ -282,11 +287,18 @@ AsmRelocateApLoopEnd: > ;-----------------------------------------------------------------------= ------------- > - > global ASM_PFX(AsmGetAddressMap) > ASM_PFX(AsmGetAddressMap): > - mov rax, ASM_PFX(RendezvousFunnelProc) > + ; Save absolute address of InitializeFloatingPointUnits() in data el= ement > + ; within the RendezvousFunnelProc template. This provides the addre= ss of > + ; the InitializeFloatingPointUnits() function to the RendezvousFunne= lProc > + ; after it has been copied below 1MB > + lea rax, [ASM_PFX(InitializeFloatingPointUnits)] > + mov qword [InitialzeFloatingPointUnitsAddress], rax > + > + lea rax, [ASM_PFX(RendezvousFunnelProc)] > mov qword [rcx], rax > mov qword [rcx + 8h], LongModeStart - RendezvousFunnelProcSt= art > mov qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFu= nnelProcStart > - mov rax, ASM_PFX(AsmRelocateApLoop) > + lea rax, [ASM_PFX(AsmRelocateApLoop)] > mov qword [rcx + 18h], rax > mov qword [rcx + 20h], AsmRelocateApLoopEnd - AsmRelocateApLo= opStart > ret > -- > 2.6.3.windows.1