From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D55FE21CE73F7 for ; Thu, 6 Jul 2017 09:34:07 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jul 2017 09:35:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,318,1496127600"; d="scan'208";a="123355641" Received: from orsmsx106.amr.corp.intel.com ([10.22.225.133]) by fmsmga005.fm.intel.com with ESMTP; 06 Jul 2017 09:35:48 -0700 Received: from orsmsx151.amr.corp.intel.com (10.22.226.38) by ORSMSX106.amr.corp.intel.com (10.22.225.133) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 6 Jul 2017 09:35:47 -0700 Received: from orsmsx113.amr.corp.intel.com ([169.254.9.9]) by ORSMSX151.amr.corp.intel.com ([169.254.7.140]) with mapi id 14.03.0319.002; Thu, 6 Jul 2017 09:35:47 -0700 From: "Kinney, Michael D" To: Leo Duran , "edk2-devel@lists.01.org" , "Kinney, Michael D" CC: "Justen, Jordan L" , "Fan, Jeff" , "Gao, Liming" Thread-Topic: [edk2] [PATCH v3] UefiCpuPkg: ApicLib Thread-Index: AQHS9mbnIfRk/H8kaE2sNSMF77lOJ6JHVjsA//+nzkA= Date: Thu, 6 Jul 2017 16:35:47 +0000 Message-ID: References: <1499352472-7348-1-git-send-email-leo.duran@amd.com> <1499352472-7348-2-git-send-email-leo.duran@amd.com> In-Reply-To: <1499352472-7348-2-git-send-email-leo.duran@amd.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Subject: Re: [PATCH v3] UefiCpuPkg: ApicLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Jul 2017 16:34:08 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Leo, Some of the change here do not follow the coding standard. For function ca= lls with many arguments,=20 either put the function call on a single line, or break it up with each arg= on its own line. This was clarified in the latest version of the EDK II C Coding Standard. https://bugzilla.tianocore.org/show_bug.cgi?id=3D425 https://github.com/tianocore-docs/edk2-CCodingStandardsSpecification/commit= /3f1100beda60843361a9761b43ba7b18adf0d265 Mike -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Leo = Duran Sent: Thursday, July 6, 2017 7:48 AM To: edk2-devel@lists.01.org Cc: Justen, Jordan L ; Leo Duran ; Fan, Jeff ; Gao, Liming Subject: [edk2] [PATCH v3] UefiCpuPkg: ApicLib GetProcessorLocationByApicId () - Adjust InitialApicId to properly concatenate Package on AMD processor. - Clean-ups on C Coding standards. Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 42 +++++++++++++-----= ---- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 40 ++++++++++++------= --- 2 files changed, 49 insertions(+), 33 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Li= brary/BaseXApicLib/BaseXApicLib.c index 2091e5e..ce6d9d7 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -48,7 +48,7 @@ StandardSignatureIsAuthenticAMD ( UINT32 RegEcx; UINT32 RegEdx; =20 - AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); @@ -338,7 +338,7 @@ GetInitialApicId ( AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); =20 // - // If CPUID Leaf B is supported,=20 + // If CPUID Leaf B is supported, // And CPUID.0BH:EBX[15:0] reports a non-zero value, // Then the initial 32-bit APIC ID =3D CPUID.0BH:EDX // Else the initial 8-bit APIC ID =3D CPUID.1:EBX[31:24] @@ -1013,13 +10= 13,14 @@ GetProcessorLocationByApicId ( UINT32 MaxCoresPerNode; UINT32 CorePerNodeMask; UINT32 ApicIdShift; + UINT32 ApicIdMask; UINTN ThreadBits; UINTN CoreBits; =20 // // Check if the processor is capable of supporting more than one logical= processor. // - AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL,=20 + &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { if (Thread !=3D NULL) { *Thread =3D 0; @@ -1042,8 +1043,8 @@ GetProcessorLocationByApicId ( // // Get max index of CPUID // - AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); - AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NU= LL); + AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); =20 + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL,=20 + NULL); =20 // // If the extended topology enumeration leaf is available, it @@ -1051,7= +1052,7 @@ GetProcessorLocationByApicId ( // TopologyLeafSupported =3D FALSE; if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { - AsmCpuidEx( + AsmCpuidEx ( CPUID_EXTENDED_TOPOLOGY, 0, &ExtendedTopologyEax.Uint32, @@ -1072,7 +1073,7 @@ GetProcessorLocationByApicId ( // the SMT sub-field of x2APIC ID. // LevelType =3D ExtendedTopologyEcx.Bits.LevelType; - ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); + ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; =20 // @@ -1081,7 +1082,7 @@ GetProcessorLocationByApicId ( // SubIndex =3D 1; do { - AsmCpuidEx( + AsmCpuidEx ( CPUID_EXTENDED_TOPOLOGY, SubIndex, &ExtendedTopologyEax.Uint32, @@ -1103,7 +1104,7 @@ GetProcessorLocationByApicId ( // // Get logical processor count // - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL)= ; + AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,=20 + NULL); MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; =20 // @@ -1114,11 +1115,11 @@ GetProcessorLocationByApicId ( // // Check for topology extensions on AMD processor // - if (StandardSignatureIsAuthenticAMD()) { + if (StandardSignatureIsAuthenticAMD ()) { if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { - AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx= .Uint32, NULL); + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL,=20 + &AmdExtendedCpuSigEcx.Uint32, NULL); if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { - AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopolo= gyEbx.Uint32, + AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL,=20 + &AmdProcessorTopologyEbx.Uint32, &AmdProcessorTopologyEcx.Uint32, NULL); // // Get cores per processor package @@ -1128,7 +1129,7 @@ GetProc= essorLocationByApicId ( // // Account for actual thread count (e.g., SMT disabled) // - AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddre= ssSizeEcx.Uint32, NULL); + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL,=20 + &AmdVirPhyAddressSizeEcx.Uint32, NULL); MaxThreadPerPackageMask =3D 1 << AmdVirPhyAddressSizeEcx.Bits.Ap= icIdCoreIdSize; ActualThreadPerPackageMask =3D 1; while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage= ) { @@ -1136,7 +1137,7 @@ GetProcessorLocationByApicId ( } =20 // - // Adjust APIC Id to report concatenation of Package|Core|Thread= . + // Adjust APIC Id to report concatenation of Core|Thread. // if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { MaxCoresPerNode =3D MaxCoresPerPackage / (AmdProcessorTopology= Ecx.Bits.NodesPerProcessor + 1); @@ -1148,13 +1149,20 @@ GetProcessorLocati= onByApicId ( CorePerNodeMask -=3D 1; =20 ApicIdShift =3D 0; + ApicIdMask =3D ActualThreadPerPackageMask; do { ApicIdShift +=3D 1; - ActualThreadPerPackageMask <<=3D 1; - } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask)= ; + ApicIdMask <<=3D 1; + } while (ApicIdMask < MaxThreadPerPackageMask); =20 InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> ApicI= dShift) | (InitialApicId & CorePerNodeMask); } + // + // Adjust APIC Id to report concatenation of Package|Core|Thread= . + // + if ((InitialApicId & ~(MaxThreadPerPackageMask - 1)) !=3D 0) { + InitialApicId =3D (InitialApicId & (ActualThreadPerPackageMask= - 1)) | ActualThreadPerPackageMask; + } } } } @@ -1163,7 +1171,7 @@ GetProcessorLocationByApicId ( // Extract core count based on CACHE information // if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NU= LL, NULL); + AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,=20 + NULL, NULL, NULL); if (CacheParamsEax.Uint32 !=3D 0) { MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIds= ForLogicalProcessors + 1; } diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index d5d4efa..54ea492 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -49,7 +49,7 @@ StandardSignatureIsAuthenticAMD ( UINT32 RegEcx; UINT32 RegEdx; =20 - AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); @@ -1108,13 +1108,14 @@ GetProcessorLocationByApicId ( UINT32 MaxCoresPerNode; UINT32 CorePerNodeMask; UINT32 ApicIdShift; + UINT32 ApicIdMask; UINTN ThreadBits; UINTN CoreBits; =20 // // Check if the processor is capable of supporting more than one logical= processor. // - AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL,=20 + &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { if (Thread !=3D NULL) { *Thread =3D 0; @@ -1137,8 +1138,8 @@ GetProcessorLocationByApicId ( // // Get max index of CPUID // - AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); - AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NU= LL); + AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); =20 + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL,=20 + NULL); =20 // // If the extended topology enumeration leaf is available, it @@ -1146,7= +1147,7 @@ GetProcessorLocationByApicId ( // TopologyLeafSupported =3D FALSE; if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { - AsmCpuidEx( + AsmCpuidEx ( CPUID_EXTENDED_TOPOLOGY, 0, &ExtendedTopologyEax.Uint32, @@ -1167,7 +1168,7 @@ GetProcessorLocationByApicId ( // the SMT sub-field of x2APIC ID. // LevelType =3D ExtendedTopologyEcx.Bits.LevelType; - ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); + ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; =20 // @@ -1176,7 +1177,7 @@ GetProcessorLocationByApicId ( // SubIndex =3D 1; do { - AsmCpuidEx( + AsmCpuidEx ( CPUID_EXTENDED_TOPOLOGY, SubIndex, &ExtendedTopologyEax.Uint32, @@ -1198,7 +1199,7 @@ GetProcessorLocationByApicId ( // // Get logical processor count // - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL)= ; + AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,=20 + NULL); MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; =20 // @@ -1209,11 +1210,11 @@ GetProcessorLocationByApicId ( // // Check for topology extensions on AMD processor // - if (StandardSignatureIsAuthenticAMD()) { + if (StandardSignatureIsAuthenticAMD ()) { if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { - AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx= .Uint32, NULL); + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL,=20 + &AmdExtendedCpuSigEcx.Uint32, NULL); if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { - AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopolo= gyEbx.Uint32, + AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL,=20 + &AmdProcessorTopologyEbx.Uint32, &AmdProcessorTopologyEcx.Uint32, NULL); // // Get cores per processor package @@ -1223,7 +1224,7 @@ GetProc= essorLocationByApicId ( // // Account for actual thread count (e.g., SMT disabled) // - AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddre= ssSizeEcx.Uint32, NULL); + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL,=20 + &AmdVirPhyAddressSizeEcx.Uint32, NULL); MaxThreadPerPackageMask =3D 1 << AmdVirPhyAddressSizeEcx.Bits.Ap= icIdCoreIdSize; ActualThreadPerPackageMask =3D 1; while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage= ) { @@ -1231,7 +1232,7 @@ GetProcessorLocationByApicId ( } =20 // - // Adjust APIC Id to report concatenation of Package|Core|Thread= . + // Adjust APIC Id to report concatenation of Core|Thread. // if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { MaxCoresPerNode =3D MaxCoresPerPackage / (AmdProcessorTopology= Ecx.Bits.NodesPerProcessor + 1); @@ -1243,13 +1244,20 @@ GetProcessorLocati= onByApicId ( CorePerNodeMask -=3D 1; =20 ApicIdShift =3D 0; + ApicIdMask =3D ActualThreadPerPackageMask; do { ApicIdShift +=3D 1; - ActualThreadPerPackageMask <<=3D 1; - } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask)= ; + ApicIdMask <<=3D 1; + } while (ApicIdMask < MaxThreadPerPackageMask); =20 InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> ApicI= dShift) | (InitialApicId & CorePerNodeMask); } + // + // Adjust APIC Id to report concatenation of Package|Core|Thread= . + // + if ((InitialApicId & ~(MaxThreadPerPackageMask - 1)) !=3D 0) { + InitialApicId =3D (InitialApicId & (ActualThreadPerPackageMask= - 1)) | ActualThreadPerPackageMask; + } } } } @@ -1258,7 +1266,7 @@ GetProcessorLocationByApicId ( // Extract core count based on CACHE information // if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NU= LL, NULL); + AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,=20 + NULL, NULL, NULL); if (CacheParamsEax.Uint32 !=3D 0) { MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIds= ForLogicalProcessors + 1; } -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel