From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=michael.d.kinney@intel.com; receiver=edk2-devel@lists.01.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 736A4222CF1C8 for ; Wed, 10 Jan 2018 13:52:49 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jan 2018 13:58:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,342,1511856000"; d="scan'208";a="165775544" Received: from orsmsx101.amr.corp.intel.com ([10.22.225.128]) by orsmga004.jf.intel.com with ESMTP; 10 Jan 2018 13:58:01 -0800 Received: from orsmsx159.amr.corp.intel.com (10.22.240.24) by ORSMSX101.amr.corp.intel.com (10.22.225.128) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 10 Jan 2018 13:58:00 -0800 Received: from orsmsx113.amr.corp.intel.com ([169.254.9.187]) by ORSMSX159.amr.corp.intel.com ([169.254.11.33]) with mapi id 14.03.0319.002; Wed, 10 Jan 2018 13:58:00 -0800 From: "Kinney, Michael D" To: "Gao, Liming" , "edk2-devel@lists.01.org" , "Kinney, Michael D" CC: Andrew Fish , "Yao, Jiewen" , "Dong, Eric" , Laszlo Ersek Thread-Topic: [Patch 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain Thread-Index: AQHTiidt35DvauSQJEutcEPk9RVF8KNtewxAgAAsIdA= Date: Wed, 10 Jan 2018 21:57:59 +0000 Message-ID: References: <20180110152432.15964-1-liming.gao@intel.com> <20180110152432.15964-5-liming.gao@intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Subject: Re: [Patch 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Jan 2018 21:52:49 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Liming, Here is a previous patch email series that demonstrates=20 this technique. https://lists.01.org/pipermail/edk2-devel/2017-September/015109.html https://github.com/tianocore/edk2/commit/4c34a8ea191155f438901e635bd8781007= 2b19a4#diff-5d3b0f5982124c722c30f6d0e6b8711d Thanks, Mike > -----Original Message----- > From: Kinney, Michael D > Sent: Wednesday, January 10, 2018 11:22 AM > To: Gao, Liming ; edk2- > devel@lists.01.org; Kinney, Michael D > > Cc: Andrew Fish ; Yao, Jiewen > ; Dong, Eric ; > Laszlo Ersek > Subject: RE: [Patch 4/7] UefiCpuPkg: Update > CpuExceptionHandlerLib pass XCODE5 tool chain >=20 > Liming, >=20 > Can we use NASM syntax for instructions instead of db > bytes? >=20 > If you put the label for the fixup after the instruction, > you > can patch by subtracting the size of the patch value from > the > label. >=20 > For example, instead of: >=20 > > + db 0x48, 0xB8 > > +JmpAbsoluteAddress: > > + dq 0 ; mov rax, > HookAfterStubHeaderEnd >=20 > Use: >=20 > movq rax, 0 > JmpAbsoluteAddress: >=20 > And in the patch loop: >=20 > mov qword [rcx + (JmpAbsoluteAddress - 8 - > HookAfterStubHeaderBegin)], rax >=20 >=20 > If this works, then please use this technique to remove > use of db for instructions throughout this series. >=20 > Mike >=20 > > -----Original Message----- > > From: Gao, Liming > > Sent: Wednesday, January 10, 2018 7:24 AM > > To: edk2-devel@lists.01.org > > Cc: Andrew Fish ; Yao, Jiewen > > ; Dong, Eric > ; > > Laszlo Ersek ; Kinney, Michael D > > > > Subject: [Patch 4/7] UefiCpuPkg: Update > > CpuExceptionHandlerLib pass XCODE5 tool chain > > > > Use the dummy address as jmp destination, and add the > > logic to fix up > > the address to the absolute address at boot time. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Liming Gao > > Cc: Andrew Fish > > Cc: Jiewen Yao > > Cc: Eric Dong > > Cc: Laszlo Ersek > > Cc: Michael Kinney > > --- > > .../X64/ExceptionHandlerAsm.nasm | > 29 > > ++++++++++++++++------ > > 1 file changed, 22 insertions(+), 7 deletions(-) > > > > diff --git > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception > > HandlerAsm.nasm > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception > > HandlerAsm.nasm > > index ba8993d84b..a5fde0a875 100644 > > --- > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception > > HandlerAsm.nasm > > +++ > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception > > HandlerAsm.nasm > > @@ -1,5 +1,5 @@ > > ;----------------------------------------------------- > -- > > ----------------------- ; > > -; Copyright (c) 2012 - 2014, Intel Corporation. All > > rights reserved.
> > +; Copyright (c) 2012 - 2018, Intel Corporation. All > > rights reserved.
> > ; This program and the accompanying materials > > ; are licensed and made available under the terms and > > conditions of the BSD License > > ; which accompanies this distribution. The full text > of > > the license may be found at > > @@ -40,7 +40,8 @@ AsmIdtVectorBegin: > > db 0x6a ; push #VectorNum > > db ($ - AsmIdtVectorBegin) / > ((AsmIdtVectorEnd > > - AsmIdtVectorBegin) / 32) ; VectorNum > > push rax > > - mov rax, ASM_PFX(CommonInterruptEntry) > > + db 0x48, 0xB8 > > + dq 0 ; mov rax, > > ASM_PFX(CommonInterruptEntry) > > jmp rax > > %endrep > > AsmIdtVectorEnd: > > @@ -50,7 +51,9 @@ HookAfterStubHeaderBegin: > > @VectorNum: > > db 0 ; 0 will be fixed > > push rax > > - mov rax, HookAfterStubHeaderEnd > > + db 0x48, 0xB8 > > +JmpAbsoluteAddress: > > + dq 0 ; mov rax, > HookAfterStubHeaderEnd > > jmp rax > > HookAfterStubHeaderEnd: > > mov rax, rsp > > @@ -260,8 +263,7 @@ HasErrorCode: > > ; and make sure RSP is 16-byte aligned > > ; > > sub rsp, 4 * 8 + 8 > > - mov rax, ASM_PFX(CommonExceptionHandler) > > - call rax > > + call ASM_PFX(CommonExceptionHandler) > > add rsp, 4 * 8 + 8 > > > > cli > > @@ -369,11 +371,24 @@ DoIret: > > ; comments here for definition of address map > > global ASM_PFX(AsmGetTemplateAddressMap) > > ASM_PFX(AsmGetTemplateAddressMap): > > - mov rax, AsmIdtVectorBegin > > + lea rax, [AsmIdtVectorBegin] > > mov qword [rcx], rax > > mov qword [rcx + 0x8], (AsmIdtVectorEnd - > > AsmIdtVectorBegin) / 32 > > - mov rax, HookAfterStubHeaderBegin > > + lea rax, [HookAfterStubHeaderBegin] > > mov qword [rcx + 0x10], rax > > + > > +; Fix up CommonInterruptEntry address > > + lea rax, [ASM_PFX(CommonInterruptEntry)] > > + lea rcx, [AsmIdtVectorBegin] > > +%rep 32 > > + mov qword [rcx + (JmpAbsoluteAddress - > > HookAfterStubHeaderBegin)], rax > > + add rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin) > / > > 32 > > +%endrep > > +; Fix up HookAfterStubHeaderEnd > > + lea rax, [HookAfterStubHeaderEnd] > > + lea rcx, [JmpAbsoluteAddress] > > + mov qword [rcx], rax > > + > > ret > > > > ;----------------------------------------------------- > -- > > ------------------------------ > > -- > > 2.11.0.windows.1