From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 37D8F802B4 for ; Sun, 5 Mar 2017 17:40:14 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Mar 2017 17:40:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,251,1484035200"; d="scan'208";a="1105106742" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga001.jf.intel.com with ESMTP; 05 Mar 2017 17:40:13 -0800 Received: from fmsmsx112.amr.corp.intel.com (10.18.116.6) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sun, 5 Mar 2017 17:40:13 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX112.amr.corp.intel.com (10.18.116.6) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sun, 5 Mar 2017 17:40:04 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.132]) with mapi id 14.03.0248.002; Mon, 6 Mar 2017 09:40:02 +0800 From: "Dong, Eric" To: "Wu, Hao A" , "edk2-devel@lists.01.org" CC: "Tian, Feng" , "Zhang, Chao B" Thread-Topic: [PATCH v3 09/12] SecurityPkg/Opal: Refine casting expression result to bigger size Thread-Index: AQHSjyXbSZe6BQXrV06SIf0iafcc2KGHFseA Date: Mon, 6 Mar 2017 01:40:02 +0000 Message-ID: References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> <1487999555-9764-10-git-send-email-hao.a.wu@intel.com> In-Reply-To: <1487999555-9764-10-git-send-email-hao.a.wu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v3 09/12] SecurityPkg/Opal: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Mar 2017 01:40:14 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong -----Original Message----- From: Wu, Hao A=20 Sent: Saturday, February 25, 2017 1:13 PM To: edk2-devel@lists.01.org Cc: Wu, Hao A; Dong, Eric; Tian, Feng; Zhang, Chao B Subject: [PATCH v3 09/12] SecurityPkg/Opal: Refine casting expression resul= t to bigger size There are cases that the operands of an expression are all with rank less t= han UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like //= UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflo= w within the rank of "int" (integer promotions) and the result is then cast= to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove = the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with ra= nk less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch,= level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Eric Dong Cc: Feng Tian Cc: Chao Zhang Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu --- SecurityPkg/Tcg/Opal/OpalPasswordSmm/OpalNvmeMode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/SecurityPkg/Tcg/Opal/OpalPasswordSmm/OpalNvmeMode.c b/Security= Pkg/Tcg/Opal/OpalPasswordSmm/OpalNvmeMode.c index 9e90d54..a47d276 100644 --- a/SecurityPkg/Tcg/Opal/OpalPasswordSmm/OpalNvmeMode.c +++ b/SecurityPkg/Tcg/Opal/OpalPasswordSmm/OpalNvmeMode.c @@ -1,7 +1,7 @@ /** @file Provide functions to initialize NVME controller and perform NVME command= s =20 -Copyright (c) 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -52,7 +52,= 7 @@ enum { /// /// All of base memories are 4K(0x1000) alignment /// -#define NVME_MEM_BASE(Nvme) (Nvme->BaseMem) +#define NVME_MEM_BASE(Nvme) ((UINTN)(Nvme->BaseMem)) #define NVME_CONTROL_DATA_BASE(Nvme) (ALIGN (NVME_MEM_BASE(Nvme) + = ((NvmeGetBaseMemPages (BASEMEM_CONTROLLER_DATA)) * E= FI_PAGE_SIZE), EFI_PAGE_SIZE)) #define NVME_NAMESPACE_DATA_BASE(Nvme) (ALIGN (NVME_MEM_BASE(Nvme) + = ((NvmeGetBaseMemPages (BASEMEM_IDENTIFY_DATA)) * E= FI_PAGE_SIZE), EFI_PAGE_SIZE)) #define NVME_ASQ_BASE(Nvme) (ALIGN (NVME_MEM_BASE(Nvme) + = ((NvmeGetBaseMemPages (BASEMEM_ASQ)) * E= FI_PAGE_SIZE), EFI_PAGE_SIZE)) -- 1.9.5.msysgit.0