From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4CCA221CFA5E1 for ; Wed, 16 Aug 2017 20:20:45 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 16 Aug 2017 20:23:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,385,1498546800"; d="scan'208";a="119889453" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga004.jf.intel.com with ESMTP; 16 Aug 2017 20:23:11 -0700 Received: from fmsmsx154.amr.corp.intel.com (10.18.116.70) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 16 Aug 2017 20:23:11 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX154.amr.corp.intel.com (10.18.116.70) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 16 Aug 2017 20:23:11 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.183]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.135]) with mapi id 14.03.0319.002; Thu, 17 Aug 2017 11:23:09 +0800 From: "Dong, Eric" To: "Kinney, Michael D" , "edk2-devel@lists.01.org" Thread-Topic: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add CPUID MCA support check Thread-Index: AQHTFwGFS6Q+ueKtVUCzedHmKtDtIKKH4gBg Date: Thu, 17 Aug 2017 03:23:09 +0000 Message-ID: References: <20170817023532.5380-1-michael.d.kinney@intel.com> In-Reply-To: <20170817023532.5380-1-michael.d.kinney@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add CPUID MCA support check X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 03:20:45 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong -----Original Message----- From: Kinney, Michael D=20 Sent: Thursday, August 17, 2017 10:36 AM To: edk2-devel@lists.01.org Cc: Dong, Eric ; Kinney, Michael D Subject: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add CPUID MCA support check https://bugzilla.tianocore.org/show_bug.cgi?id=3D674 Add CPUID check to see if the CPU supports the Machine Check Architecture b= efore accessing the Machine Check Architecture related MSRs. Cc: Eric Dong Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Kinney --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index 6b66c49085..f086b97c30 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -27,6 +27,7 @@ SMM_CPU_SEMAPHORES mSmmCpuSemaph= ores; UINTN mSemaphoreSize; SPIN_LOCK *mPFLock =3D NULL; SMM_CPU_SYNC_MODE mCpuSmmSyncMode; +BOOLEAN mMachineCheckSupported =3D FAL= SE; =20 /** Performs an atomic compare exchange operation to get semaphore. @@ -264,8 +265,12 @@ SmmWaitForApArrival ( =20 ASSERT (*mSmmMpSyncData->Counter <=3D mNumberOfCpus); =20 - LmceEn =3D IsLmceOsEnabled (); - LmceSignal =3D IsLmceSignaled(); + LmceEn =3D FALSE; + LmceSignal =3D FALSE; + if (mMachineCheckSupported) { + LmceEn =3D IsLmceOsEnabled (); + LmceSignal =3D IsLmceSignaled(); + } =20 // // Platform implementor should choose a timeout value appropriately: @@ -1366,6 +1371,13 @@ InitializeMpServiceData ( UINTN Index; UINT8 *GdtTssTables; UINTN GdtTableStepSize; + CPUID_VERSION_INFO_EDX RegEdx; + + // + // Determine if this CPU supports machine check // AsmCpuid=20 + (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx.Uint32); =20 + mMachineCheckSupported =3D (BOOLEAN)(RegEdx.Bits.MCA =3D=3D 1); =20 // // Allocate memory for all locks and semaphores -- 2.13.1.windows.2