From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.88; helo=mga01.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 50CA321F303F9 for ; Thu, 28 Sep 2017 20:07:27 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Sep 2017 20:10:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,451,1500966000"; d="scan'208";a="1200282339" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga001.fm.intel.com with ESMTP; 28 Sep 2017 20:10:42 -0700 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 28 Sep 2017 20:10:42 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 28 Sep 2017 20:10:41 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.175]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.213]) with mapi id 14.03.0319.002; Fri, 29 Sep 2017 11:10:40 +0800 From: "Dong, Eric" To: "Ruffin, Chris" , "edk2-devel@lists.01.org" CC: "Kinney, Michael D" , "Yao, Jiewen" Thread-Topic: [edk2] [PATCH] UefiCpuPkg/SmmCpuFeaturesLib: replace hard-coded machine code Thread-Index: AQHTMwztfNfHglM9bEuZetqaTMvVwKLJDHYAgAIuBCA= Date: Fri, 29 Sep 2017 03:10:39 +0000 Message-ID: References: <20170921190706.53108-1-chris.ruffin@intel.com> <20170928015144.386548-1-chris.ruffin@intel.com> In-Reply-To: <20170928015144.386548-1-chris.ruffin@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg/SmmCpuFeaturesLib: replace hard-coded machine code X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Sep 2017 03:07:27 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Chris, Thanks to provide this change. I have confirmed no binary change after this= patch.=20 Pushed this patch: SHA-1: 4c34a8ea191155f438901e635bd87810072b19a4 * UefiCpuPkg/SmmCpuFeaturesLib: replace hard-coded machine code Replace hard-coded machine code with equivalent assembly source code. Changes tested by checking for machine code equivalence by disassembling the original and changed code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chris Ruffin Cc: Jiewen Yao Cc: Michael D Kinney Reviewed-by: Eric Dong Thanks, Eric -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Chri= s Ruffin Sent: Thursday, September 28, 2017 9:52 AM To: edk2-devel@lists.01.org Cc: Kinney, Michael D ; Yao, Jiewen Subject: [edk2] [PATCH] UefiCpuPkg/SmmCpuFeaturesLib: replace hard-coded ma= chine code Replace hard-coded machine code with equivalent assembly source code. Changes tested by checking for machine code equivalence by disassembling th= e original and changed code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chris Ruffin Cc: Jiewen Yao Cc: Michael D Kinney --- .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 24 ++++++++++-------- .../SmmCpuFeaturesLib/Ia32/SmiException.nasm | 5 ++-- .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 29 ++++++++++++------= ---- .../SmmCpuFeaturesLib/X64/SmiException.nasm | 5 ++-- 4 files changed, 34 insertions(+), 29 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm b/Uefi= CpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm index b1c84a494f..00c0f0672c 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2017, Intel Corporation. All rights=20 +reserved.
; This program and the accompanying materials ; are licensed and made ava= ilable under the terms and conditions of the BSD License ; which accompani= es this distribution. The full text of the license may be found at @@ -51,= 6 +51,11 @@ global ASM_PFX(gStmSmbase) global ASM_PFX(gStmXdSupported) ex= tern ASM_PFX(gStmSmiHandlerIdtr) =20 +ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4 +ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4 +ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4 +ASM_PFX(gStmXdSupported) EQU StmXdSupportedPatch - 1 + SECTION .text =20 BITS 16 @@ -66,8 +71,8 @@ _StmSmiEntryPoint: o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx] mov ax, PROTECT_MODE_CS mov [cs:bx-0x2],ax - DB 0x66, 0xbf ; mov edi, SMBASE -ASM_PFX(gStmSmbase): DD 0 +o32 mov edi, strict dword 0 +StmSmbasePatch: lea eax, [edi + (@32bit - _StmSmiEntryPoint) + 0x8000] mov [cs:bx-0x6],eax mov ebx, cr0 @@ -87,15 +92,15 @@ o16 mov es, ax o16 mov fs, ax o16 mov gs, ax o16 mov ss, ax - DB 0xbc ; mov esp, imm32 -ASM_PFX(gStmSmiStack): DD 0 + mov esp, strict dword 0 +StmSmiStackPatch: mov eax, ASM_PFX(gStmSmiHandlerIdtr) lidt [eax] jmp ProtFlatMode =20 ProtFlatMode: - DB 0xb8 ; mov eax, imm32 -ASM_PFX(gStmSmiCr3): DD 0 + mov eax, strict dword 0 +StmSmiCr3Patch: mov cr3, eax ; ; Need to test for CR4 specific bit support @@ -134,8 +139,8 @@ ASM_PFX(gS= tmSmiCr3): DD 0 .6: =20 ; enable NXE if supported - DB 0b0h ; mov al, imm8 -ASM_PFX(gStmXdSupported): DB 1 + mov al, strict byte 1 +StmXdSupportedPatch: cmp al, 0 jz @SkipXd ; @@ -268,4 +273,3 @@ _StmSmiHandler: =20 ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPo= int - diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm b/= UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm index 0ce8501ba9..93dc3005b7 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserve= d.
+; Copyright (c) 2009 - 2017, Intel Corporation. All rights=20 +reserved.
; This program and the accompanying materials ; are licensed and made ava= ilable under the terms and conditions of the BSD License ; which accompani= es this distribution. The full text of the license may be found at @@ -87,= 7 +87,7 @@ ASM_PFX(OnException): =20 mov ebx, eax mov eax, 4 - DB 0x0f, 0x01, 0x0c1 ; VMCALL + vmcall jmp $ =20 global ASM_PFX(OnStmSetup) @@ -173,4 +173,3 @@ ASM_PFX(OnStmTeardown): =20 .72: rsm - diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm b/UefiC= puPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm index c801591fc7..bcac643e96 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2017, Intel Corporation. All rights=20 +reserved.
; This program and the accompanying materials ; are licensed and made ava= ilable under the terms and conditions of the BSD License ; which accompani= es this distribution. The full text of the license may be found at @@ -61,= 6 +61,11 @@ global ASM_PFX(gcStmSmiHandlerTemplate) global ASM_PFX(gcStmSm= iHandlerSize) global ASM_PFX(gcStmSmiHandlerOffset) =20 +ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4 +ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4 +ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4 +ASM_PFX(gStmXdSupported) EQU StmXdSupportedPatch - 1 + DEFAULT REL SECTION .text =20 @@ -76,8 +81,8 @@ _StmSmiEntryPoint: o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx] mov ax, PROTECT_MODE_CS mov [cs:bx-0x2],ax - DB 0x66, 0xbf ; mov edi, SMBASE -ASM_PFX(gStmSmbase): DD 0 +o32 mov edi, strict dword 0 +StmSmbasePatch: lea eax, [edi + (@ProtectedMode - _StmSmiEntryPoint) + 0x8000] mov [cs:bx-0x6],eax mov ebx, cr0 @@ -97,14 +102,14 @@ o16 mov es, ax o16 mov fs, ax o16 mov gs, ax o16 mov ss, ax - DB 0xbc ; mov esp, imm32 -ASM_PFX(gStmSmiStack): DD 0 + mov esp, strict dword 0 +StmSmiStackPatch: jmp ProtFlatMode =20 BITS 64 ProtFlatMode: - DB 0xb8 ; mov eax, offset gStmSmiCr3 -ASM_PFX(gStmSmiCr3): DD 0 + mov eax, strict dword 0 +StmSmiCr3Patch: mov cr3, rax mov eax, 0x668 ; as cr4.PGE is not set here, ref= resh cr3 mov cr4, rax ; in PreModifyMtrrs() to flush TLB= . @@ -119,8 +124,8 @@ ASM_PFX(gStmSmiCr3): DD 0 ltr ax =20 ; enable NXE if supported - DB 0xb0 ; mov al, imm8 -ASM_PFX(gStmXdSupported): DB 1 + mov al, strict byte 1 +StmXdSupportedPatch: cmp al, 0 jz @SkipXd ; @@ -178,8 +183,7 @@ CommonHandler: ; Save FP registers ; sub rsp, 0x200 - DB 0x48 ; FXSAVE64 - fxsave [rsp] + fxsave64 [rsp] =20 add rsp, -0x20 =20 @@ -200,8 +204,7 @@ CommonHandler: ; ; Restore FP registers ; - DB 0x48 ; FXRSTOR64 - fxrstor [rsp] + fxrstor64 [rsp] =20 add rsp, 0x200 =20 diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm b/U= efiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm index fe1bf3f165..ce9d7c2bb6 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2017, Intel Corporation. All rights=20 +reserved.
; This program and the accompanying materials ; are licensed and made ava= ilable under the terms and conditions of the BSD License ; which accompani= es this distribution. The full text of the license may be found at @@ -86,= 7 +86,7 @@ ASM_PFX(OnException): add rsp, 0x28 mov ebx, eax mov eax, 4 - DB 0x0f, 0x01, 0x0c1 ; VMCALL + vmcall jmp $ =20 global ASM_PFX(OnStmSetup) @@ -176,4 +176,3 @@ ASM_PFX(OnStmTeardown): =20 .12: rsm - -- 2.13.3.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel