From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E9B082095B07E for ; Sun, 8 Oct 2017 21:55:46 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP; 08 Oct 2017 21:59:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,498,1500966000"; d="scan'208";a="160337378" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga005.fm.intel.com with ESMTP; 08 Oct 2017 21:59:12 -0700 Received: from fmsmsx126.amr.corp.intel.com (10.18.125.43) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 8 Oct 2017 21:59:12 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX126.amr.corp.intel.com (10.18.125.43) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 8 Oct 2017 21:59:12 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.175]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.152]) with mapi id 14.03.0319.002; Mon, 9 Oct 2017 12:59:10 +0800 From: "Dong, Eric" To: "Wu, Hao A" , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" Thread-Topic: [edk2] [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add check to void use null pointer. Thread-Index: AQHTQK1PVyryvoeRSUqchnkDhwXbNqLaWOeAgACcJRA= Date: Mon, 9 Oct 2017 04:59:09 +0000 Message-ID: References: <1507519098-14284-1-git-send-email-eric.dong@intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add check to void use null pointer. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Oct 2017 04:55:47 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hao, Agree with your suggestion, I will remove the if code when I merge the chan= ge. Thanks, Eric -----Original Message----- From: Wu, Hao A=20 Sent: Monday, October 9, 2017 11:39 AM To: Dong, Eric ; edk2-devel@lists.01.org Cc: Ni, Ruiyu Subject: RE: [edk2] [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add check to void us= e null pointer. > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of=20 > Eric Dong > Sent: Monday, October 09, 2017 11:18 AM > To: edk2-devel@lists.01.org > Cc: Ni, Ruiyu > Subject: [edk2] [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add check to void=20 > use null pointer. >=20 > Current code logic not check the pointer before use it. This may has=20 > potential issue, this patch add code to check it. >=20 > Cc: Ruiyu Ni > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Eric Dong > --- > UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 5 +++++ > 1 file changed, 5 insertions(+) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > index ef72b9b..2c1dc82 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > @@ -226,12 +226,17 @@ SetProcessorRegister ( > CPU_REGISTER_TABLE *RegisterTable; >=20 > InitApicId =3D GetInitialApicId (); > + RegisterTable =3D NULL; > for (Index =3D 0; Index < RegisterTableCount; Index++) { > if (RegisterTables[Index].InitialApicId =3D=3D InitApicId) { > RegisterTable =3D &RegisterTables[Index]; > break; > } > } > + ASSERT (RegisterTable !=3D NULL); > + if (RegisterTable =3D=3D NULL) { > + return; > + } Hi Eric, If "RegisterTable =3D=3D NULL" is a case that should never occur, my though= t is that using "ASSERT" merely is enough. The 'if' statement above seems c= an be removed for me. Best Regards, Hao Wu >=20 > // > // Traverse Register Table of this logical processor > -- > 2.7.0.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel