* [PATCH] MdeModulePkg/PciBus: Fix bug that PCI BUS claims too much resource
@ 2017-10-20 9:56 Ruiyu Ni
2017-10-23 7:16 ` Dong, Eric
0 siblings, 1 reply; 2+ messages in thread
From: Ruiyu Ni @ 2017-10-20 9:56 UTC (permalink / raw)
To: edk2-devel; +Cc: Eric Dong
The bug was caused by 728d74973c9262b6c7b7ef4be213223d55affec3
"MdeModulePkg/PciBus: Count multiple hotplug resource paddings".
The patch firstly updated the Bridge->Alignment to the maximum
alignment of all devices under the bridge, then aligned the
Bridge->Length to Bridge->Alignment.
It caused too much resources were claimed.
The new patch firstly aligns Bridge->Length to Bridge->Alignment,
then updates the Bridge->Alignment to the maximum alignment of all
devices under the bridge.
Because the step to update the Bridge->Alignment is to make sure
the resource allocated to the bus under the Bridge meets all
devices alignment. But the Bridge->Length doesn't have to align
to the maximum alignment.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
---
.../Bus/Pci/PciBusDxe/PciResourceSupport.c | 24 +++++++++++-----------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
index 8dbe9a0038..2f713fcee9 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
@@ -389,18 +389,7 @@ CalculateResourceAperture (
}
//
- // Adjust the bridge's alignment to the MAX (first) alignment of all children.
- //
- CurrentLink = Bridge->ChildList.ForwardLink;
- if (CurrentLink != &Bridge->ChildList) {
- Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
- if (Node->Alignment > Bridge->Alignment) {
- Bridge->Alignment = Node->Alignment;
- }
- }
-
- //
- // At last, adjust the aperture with the bridge's alignment
+ // Adjust the aperture with the bridge's alignment
//
Aperture[PciResUsageTypical] = ALIGN_VALUE (Aperture[PciResUsageTypical], Bridge->Alignment + 1);
Aperture[PciResUsagePadding] = ALIGN_VALUE (Aperture[PciResUsagePadding], Bridge->Alignment + 1);
@@ -410,6 +399,17 @@ CalculateResourceAperture (
// Use the larger one between the padding resource and actual occupied resource.
//
Bridge->Length = MAX (Aperture[PciResUsageTypical], Aperture[PciResUsagePadding]);
+
+ //
+ // Adjust the bridge's alignment to the MAX (first) alignment of all children.
+ //
+ CurrentLink = Bridge->ChildList.ForwardLink;
+ if (CurrentLink != &Bridge->ChildList) {
+ Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
+ if (Node->Alignment > Bridge->Alignment) {
+ Bridge->Alignment = Node->Alignment;
+ }
+ }
}
/**
--
2.12.2.windows.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] MdeModulePkg/PciBus: Fix bug that PCI BUS claims too much resource
2017-10-20 9:56 [PATCH] MdeModulePkg/PciBus: Fix bug that PCI BUS claims too much resource Ruiyu Ni
@ 2017-10-23 7:16 ` Dong, Eric
0 siblings, 0 replies; 2+ messages in thread
From: Dong, Eric @ 2017-10-23 7:16 UTC (permalink / raw)
To: Ni, Ruiyu, edk2-devel@lists.01.org
Reviewed-by: Eric Dong <eric.dong@intel.com>
> -----Original Message-----
> From: Ni, Ruiyu
> Sent: Friday, October 20, 2017 5:56 PM
> To: edk2-devel@lists.01.org
> Cc: Dong, Eric <eric.dong@intel.com>
> Subject: [PATCH] MdeModulePkg/PciBus: Fix bug that PCI BUS claims too
> much resource
>
> The bug was caused by 728d74973c9262b6c7b7ef4be213223d55affec3
> "MdeModulePkg/PciBus: Count multiple hotplug resource paddings".
>
> The patch firstly updated the Bridge->Alignment to the maximum alignment
> of all devices under the bridge, then aligned the
> Bridge->Length to Bridge->Alignment.
> It caused too much resources were claimed.
>
> The new patch firstly aligns Bridge->Length to Bridge->Alignment, then
> updates the Bridge->Alignment to the maximum alignment of all devices
> under the bridge.
> Because the step to update the Bridge->Alignment is to make sure the
> resource allocated to the bus under the Bridge meets all devices alignment.
> But the Bridge->Length doesn't have to align to the maximum alignment.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> ---
> .../Bus/Pci/PciBusDxe/PciResourceSupport.c | 24 +++++++++++----------
> -
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
> index 8dbe9a0038..2f713fcee9 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
> @@ -389,18 +389,7 @@ CalculateResourceAperture (
> }
>
> //
> - // Adjust the bridge's alignment to the MAX (first) alignment of all children.
> - //
> - CurrentLink = Bridge->ChildList.ForwardLink;
> - if (CurrentLink != &Bridge->ChildList) {
> - Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
> - if (Node->Alignment > Bridge->Alignment) {
> - Bridge->Alignment = Node->Alignment;
> - }
> - }
> -
> - //
> - // At last, adjust the aperture with the bridge's alignment
> + // Adjust the aperture with the bridge's alignment
> //
> Aperture[PciResUsageTypical] = ALIGN_VALUE
> (Aperture[PciResUsageTypical], Bridge->Alignment + 1);
> Aperture[PciResUsagePadding] = ALIGN_VALUE
> (Aperture[PciResUsagePadding], Bridge->Alignment + 1); @@ -410,6 +399,17
> @@ CalculateResourceAperture (
> // Use the larger one between the padding resource and actual occupied
> resource.
> //
> Bridge->Length = MAX (Aperture[PciResUsageTypical],
> Aperture[PciResUsagePadding]);
> +
> + //
> + // Adjust the bridge's alignment to the MAX (first) alignment of all children.
> + //
> + CurrentLink = Bridge->ChildList.ForwardLink; if (CurrentLink !=
> + &Bridge->ChildList) {
> + Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
> + if (Node->Alignment > Bridge->Alignment) {
> + Bridge->Alignment = Node->Alignment;
> + }
> + }
> }
>
> /**
> --
> 2.12.2.windows.2
^ permalink raw reply [flat|nested] 2+ messages in thread
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