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Mon, 23 Oct 2017 00:16:13 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.175]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.213]) with mapi id 14.03.0319.002; Mon, 23 Oct 2017 15:16:11 +0800 From: "Dong, Eric" To: "Ni, Ruiyu" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH] MdeModulePkg/PciBus: Fix bug that PCI BUS claims too much resource Thread-Index: AQHTSYmwA5kQpD0eQUmIvSKQd4fQgqLxCnRg Date: Mon, 23 Oct 2017 07:16:10 +0000 Message-ID: References: <20171020095608.161848-1-ruiyu.ni@intel.com> In-Reply-To: <20171020095608.161848-1-ruiyu.ni@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] MdeModulePkg/PciBus: Fix bug that PCI BUS claims too much resource X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Oct 2017 07:12:31 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong > -----Original Message----- > From: Ni, Ruiyu > Sent: Friday, October 20, 2017 5:56 PM > To: edk2-devel@lists.01.org > Cc: Dong, Eric > Subject: [PATCH] MdeModulePkg/PciBus: Fix bug that PCI BUS claims too > much resource >=20 > The bug was caused by 728d74973c9262b6c7b7ef4be213223d55affec3 > "MdeModulePkg/PciBus: Count multiple hotplug resource paddings". >=20 > The patch firstly updated the Bridge->Alignment to the maximum alignment > of all devices under the bridge, then aligned the > Bridge->Length to Bridge->Alignment. > It caused too much resources were claimed. >=20 > The new patch firstly aligns Bridge->Length to Bridge->Alignment, then > updates the Bridge->Alignment to the maximum alignment of all devices > under the bridge. > Because the step to update the Bridge->Alignment is to make sure the > resource allocated to the bus under the Bridge meets all devices alignmen= t. > But the Bridge->Length doesn't have to align to the maximum alignment. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ruiyu Ni > Cc: Eric Dong > --- > .../Bus/Pci/PciBusDxe/PciResourceSupport.c | 24 +++++++++++-----= ----- > - > 1 file changed, 12 insertions(+), 12 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c > index 8dbe9a0038..2f713fcee9 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c > @@ -389,18 +389,7 @@ CalculateResourceAperture ( > } >=20 > // > - // Adjust the bridge's alignment to the MAX (first) alignment of all c= hildren. > - // > - CurrentLink =3D Bridge->ChildList.ForwardLink; > - if (CurrentLink !=3D &Bridge->ChildList) { > - Node =3D RESOURCE_NODE_FROM_LINK (CurrentLink); > - if (Node->Alignment > Bridge->Alignment) { > - Bridge->Alignment =3D Node->Alignment; > - } > - } > - > - // > - // At last, adjust the aperture with the bridge's alignment > + // Adjust the aperture with the bridge's alignment > // > Aperture[PciResUsageTypical] =3D ALIGN_VALUE > (Aperture[PciResUsageTypical], Bridge->Alignment + 1); > Aperture[PciResUsagePadding] =3D ALIGN_VALUE > (Aperture[PciResUsagePadding], Bridge->Alignment + 1); @@ -410,6 +399,17 > @@ CalculateResourceAperture ( > // Use the larger one between the padding resource and actual occupied > resource. > // > Bridge->Length =3D MAX (Aperture[PciResUsageTypical], > Aperture[PciResUsagePadding]); > + > + // > + // Adjust the bridge's alignment to the MAX (first) alignment of all c= hildren. > + // > + CurrentLink =3D Bridge->ChildList.ForwardLink; if (CurrentLink !=3D > + &Bridge->ChildList) { > + Node =3D RESOURCE_NODE_FROM_LINK (CurrentLink); > + if (Node->Alignment > Bridge->Alignment) { > + Bridge->Alignment =3D Node->Alignment; > + } > + } > } >=20 > /** > -- > 2.12.2.windows.2