From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B3B66223972A3 for ; Tue, 6 Feb 2018 23:26:40 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Feb 2018 23:32:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,471,1511856000"; d="scan'208";a="201961654" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga005.fm.intel.com with ESMTP; 06 Feb 2018 23:32:23 -0800 Received: from fmsmsx124.amr.corp.intel.com (10.18.125.39) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 6 Feb 2018 23:32:22 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx124.amr.corp.intel.com (10.18.125.39) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 6 Feb 2018 23:32:22 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.124]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.125]) with mapi id 14.03.0319.002; Wed, 7 Feb 2018 15:32:20 +0800 From: "Dong, Eric" To: "Ni, Ruiyu" , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH] UefiCpuPkg/FeaturesLib: Fix Haswell CPU hang with 50% throttling Thread-Index: AQHTnxv4GOtOkIWoS0OmdfQNLmTQIaOYcRXw Date: Wed, 7 Feb 2018 07:32:19 +0000 Message-ID: References: <20180206072716.359712-1-ruiyu.ni@intel.com> In-Reply-To: <20180206072716.359712-1-ruiyu.ni@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg/FeaturesLib: Fix Haswell CPU hang with 50% throttling X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Feb 2018 07:26:41 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ruiy= u Ni Sent: Tuesday, February 6, 2018 3:27 PM To: edk2-devel@lists.01.org Cc: Dong, Eric Subject: [edk2] [PATCH] UefiCpuPkg/FeaturesLib: Fix Haswell CPU hang with 5= 0% throttling Today's implementation only assumes SandyBridge CPU supports Extended On-De= mand Clock Modulation Duty Cycle. Actually it is supported when CPUID.06h.EAX[5] =3D=3D 1. When platform requests 50% throttling, it causes value 1000b set to the low= -4 bits of IA32_CLOCK_MODULATION. But the wrong code sets 1000b to bits[1-3] which causes assertion. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Jeff Fan Cc: Eric Dong --- .../Library/CpuCommonFeaturesLib/ClockModulation.c | 52 ++++++++++--------= ---- 1 file changed, 23 insertions(+), 29 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c b/Ue= fiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c index 56e53561e9..84d59de78f 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c @@ -1,7 +1,7 @@ /** @file Clock Modulation feature. =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights=20 + reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -67,40 +67,34 @@ ClockModulationInitialize ( IN BOOLEAN State ) { - if (IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayM= odel)) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, - MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER, - Bits.OnDemandClockModulationDutyCycle, - PcdGet8 (PcdCpuClockModulationDutyCycle) - ); - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, - MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER, - Bits.OnDemandClockModulationEnable, - (State) ? 1 : 0 - ); - } else { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_CLOCK_MODULATION, - MSR_IA32_CLOCK_MODULATION_REGISTER, - Bits.OnDemandClockModulationDutyCycle, - PcdGet8 (PcdCpuClockModulationDutyCycle) - ); + CPUID_THERMAL_POWER_MANAGEMENT_EAX ThermalPowerManagementEax; + AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT,=20 + &ThermalPowerManagementEax.Uint32, NULL, NULL, NULL); + + CPU_REGISTER_TABLE_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_CLOCK_MODULATION, + MSR_IA32_CLOCK_MODULATION_REGISTER, + Bits.OnDemandClockModulationDutyCycle, + PcdGet8 (PcdCpuClockModulationDutyCycle) >> 1 + ); + if (ThermalPowerManagementEax.Bits.ECMD =3D=3D 1) { CPU_REGISTER_TABLE_WRITE_FIELD ( ProcessorNumber, Msr, MSR_IA32_CLOCK_MODULATION, MSR_IA32_CLOCK_MODULATION_REGISTER, - Bits.OnDemandClockModulationEnable, - (State) ? 1 : 0 + Bits.ExtendedOnDemandClockModulationDutyCycle, + PcdGet8 (PcdCpuClockModulationDutyCycle) & BIT0 ); } + CPU_REGISTER_TABLE_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_CLOCK_MODULATION, + MSR_IA32_CLOCK_MODULATION_REGISTER, + Bits.OnDemandClockModulationEnable, + (State) ? 1 : 0 + ); return RETURN_SUCCESS; } -- 2.16.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel