From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.88; helo=mga01.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E9B2422361E42 for ; Wed, 7 Feb 2018 22:58:07 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Feb 2018 23:03:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,477,1511856000"; d="scan'208";a="199587772" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga005.jf.intel.com with ESMTP; 07 Feb 2018 23:03:49 -0800 Received: from fmsmsx122.amr.corp.intel.com (10.18.125.37) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 7 Feb 2018 23:03:48 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx122.amr.corp.intel.com (10.18.125.37) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 7 Feb 2018 23:03:48 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.124]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.125]) with mapi id 14.03.0319.002; Thu, 8 Feb 2018 15:03:46 +0800 From: "Dong, Eric" To: "Ni, Ruiyu" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH] UefiCpuPkg/FeaturesLib: don't init MCi_CTL/STATUS when MCA's disabled Thread-Index: AQHToKg7gnZdWog/bE+5mc03I5LBr6OaFIYw Date: Thu, 8 Feb 2018 07:03:45 +0000 Message-ID: References: <20180208064352.156152-1-ruiyu.ni@intel.com> In-Reply-To: <20180208064352.156152-1-ruiyu.ni@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg/FeaturesLib: don't init MCi_CTL/STATUS when MCA's disabled X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Feb 2018 06:58:08 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong -----Original Message----- From: Ni, Ruiyu=20 Sent: Thursday, February 8, 2018 2:44 PM To: edk2-devel@lists.01.org Cc: Dong, Eric Subject: [PATCH] UefiCpuPkg/FeaturesLib: don't init MCi_CTL/STATUS when MCA= 's disabled Today's McaInitialize() doesn't check State value before initialize MCi_CTL= and MCi_STATUS. The patch fixes this issue by only initializing the two kinds of MSRs when = State is enabled. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Eric Dong --- .../Library/CpuCommonFeaturesLib/MachineCheck.c | 32 ++++++++++++------= ---- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiC= puPkg/Library/CpuCommonFeaturesLib/MachineCheck.c index 58dc45aeda..cc64dbbf0a 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c @@ -1,7 +1,7 @@ /** @file Machine Check features. =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights=20 + reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -140,25 +140,27 @@ McaInitialize ( MSR_IA32_MCG_CAP_REGISTER McgCap; UINT32 BankIndex; =20 - McgCap.Uint64 =3D AsmReadMsr64 (MSR_IA32_MCG_CAP); - for (BankIndex =3D 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex+= +) { - CPU_REGISTER_TABLE_WRITE64 ( - ProcessorNumber, - Msr, - MSR_IA32_MC0_CTL + BankIndex * 4, - MAX_UINT64 - ); - } - - if (PcdGetBool (PcdIsPowerOnReset)) { - for (BankIndex =3D 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex= ++) { + if (State =3D=3D TRUE) { + McgCap.Uint64 =3D AsmReadMsr64 (MSR_IA32_MCG_CAP); + for (BankIndex =3D 0; BankIndex < (UINT32) McgCap.Bits.Count;=20 + BankIndex++) { CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, - MSR_IA32_MC0_STATUS + BankIndex * 4, - 0 + MSR_IA32_MC0_CTL + BankIndex * 4, + MAX_UINT64 ); } + + if (PcdGetBool (PcdIsPowerOnReset)) { + for (BankIndex =3D 0; BankIndex < (UINTN) McgCap.Bits.Count; BankInd= ex++) { + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_MC0_STATUS + BankIndex * 4, + 0 + ); + } + } } =20 return RETURN_SUCCESS; -- 2.16.1.windows.1