From: "Dong, Eric" <eric.dong@intel.com>
To: "Wang, Jian J" <jian.j.wang@intel.com>,
"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Cc: Laszlo Ersek <lersek@redhat.com>, "Ni, Ruiyu" <ruiyu.ni@intel.com>
Subject: Re: [PATCH v2 2/4] UefiCpuPkg/CpuExceptionHandlerLib: Setup single step in #PF handler
Date: Tue, 28 Aug 2018 01:14:55 +0000 [thread overview]
Message-ID: <ED077930C258884BBCB450DB737E66224AC96735@shsmsx102.ccr.corp.intel.com> (raw)
In-Reply-To: <20180821030515.10156-3-jian.j.wang@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
> -----Original Message-----
> From: Wang, Jian J
> Sent: Tuesday, August 21, 2018 11:05 AM
> To: edk2-devel@lists.01.org
> Cc: Dong, Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>; Ni,
> Ruiyu <ruiyu.ni@intel.com>
> Subject: [PATCH v2 2/4] UefiCpuPkg/CpuExceptionHandlerLib: Setup single
> step in #PF handler
>
> > v2 changes:
> > n/a
>
> Once the #PF handler has set the page to be 'present', there should be a way
> to reset it to 'not-present'. 'TF' bit in EFLAGS can be used for this purpose. 'TF'
> bit will be set in interrupted function context so that it can be triggered once
> the cpu control returns back to the instruction causing #PF and re-execute it.
>
> This is an necessary step to implement non-stop mode for Heap Guard and
> NULL Pointer Detection feature.
>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> ---
> .../Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm | 7
> +++++++
> .../Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm | 4 +--
> -
> .../Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 4
> ++++
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.na
> sm
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.na
> sm
> index 45d6474091..6fcf5fb23f 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.na
> sm
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm
> +++ .nasm
> @@ -383,6 +383,13 @@ ErrorCodeAndVectorOnStack:
> pop dword [ebp - 4]
> mov esp, ebp
> pop ebp
> +
> +; Enable TF bit after page fault handler runs
> + cmp dword [esp], 14 ; #PF?
> + jne .5
> + bts dword [esp + 16], 8 ; EFLAGS
> +
> +.5:
> add esp, 8
> cmp dword [esp - 16], 0 ; check
> EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
> jz DoReturn
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.n
> asm
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.n
> asm
> index 62bcedea1a..7aac29c7e7 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.n
> asm
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAs
> +++ m.nasm
> @@ -355,10 +355,8 @@ o16 mov [ecx + IA32_TSS._SS], ax
> movzx ebx, word [ecx + IA32_TSS._CS]
> mov [eax - 0x8], ebx ; create CS in old stack
> mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> - bts ebx, 8
> + bts ebx, 8 ; Set TF
> mov [eax - 0x4], ebx ; create eflags in old stack
> - mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old TSS
> - mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
> sub eax, 0xc ; minus 12 byte
> mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer
>
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.na
> sm
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.na
> sm
> index 7b97810d10..f842af2336 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.na
> sm
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.
> +++ nasm
> @@ -336,6 +336,10 @@ HasErrorCode:
> pop r15
>
> mov rsp, rbp
> + cmp qword [rbp + 8], 14 ; #PF?
> + jne .1
> + bts qword [rsp + 40], 8 ; RFLAGS.TF
> +.1:
> pop rbp
> add rsp, 16
> cmp qword [rsp - 32], 0 ; check
> EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
> --
> 2.16.2.windows.1
next prev parent reply other threads:[~2018-08-28 1:15 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-21 3:05 [PATCH v2 0/4] Support non-stop mode in heap guard and null detection Jian J Wang
2018-08-21 3:05 ` [PATCH v2 1/4] MdeModulePkg/MdeModulePkg.dec: add new settings for PCDs Jian J Wang
2018-08-21 3:05 ` [PATCH v2 2/4] UefiCpuPkg/CpuExceptionHandlerLib: Setup single step in #PF handler Jian J Wang
2018-08-21 14:39 ` Laszlo Ersek
2018-08-28 1:14 ` Dong, Eric [this message]
2018-08-28 3:24 ` Wang, Jian J
2018-08-21 3:05 ` [PATCH v2 3/4] UefiCpuPkg/CpuDxe: implement non-stop mode for uefi Jian J Wang
2018-08-21 14:58 ` Laszlo Ersek
2018-08-22 7:13 ` Wang, Jian J
2018-08-22 7:45 ` Laszlo Ersek
2018-08-21 3:05 ` [PATCH v2 4/4] UefiCpuPkg/PiSmmCpuDxeSmm: implement non-stop mode for SMM Jian J Wang
2018-08-21 15:44 ` Laszlo Ersek
2018-08-22 7:16 ` Wang, Jian J
2018-08-21 14:28 ` [PATCH v2 0/4] Support non-stop mode in heap guard and null detection Laszlo Ersek
2018-08-22 6:59 ` Wang, Jian J
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ED077930C258884BBCB450DB737E66224AC96735@shsmsx102.ccr.corp.intel.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox