From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4BC9A21A02937 for ; Mon, 27 Aug 2018 18:15:00 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Aug 2018 18:14:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,297,1531810800"; d="scan'208";a="65663240" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga007.fm.intel.com with ESMTP; 27 Aug 2018 18:14:58 -0700 Received: from fmsmsx112.amr.corp.intel.com (10.18.116.6) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 27 Aug 2018 18:14:58 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX112.amr.corp.intel.com (10.18.116.6) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 27 Aug 2018 18:14:57 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.226]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.150]) with mapi id 14.03.0319.002; Tue, 28 Aug 2018 09:14:56 +0800 From: "Dong, Eric" To: "Wang, Jian J" , "edk2-devel@lists.01.org" CC: Laszlo Ersek , "Ni, Ruiyu" Thread-Topic: [PATCH v2 2/4] UefiCpuPkg/CpuExceptionHandlerLib: Setup single step in #PF handler Thread-Index: AQHUOPvZj/Ti3FZEoUC68X+nM9fXm6TUZwaQ Date: Tue, 28 Aug 2018 01:14:55 +0000 Message-ID: References: <20180821030515.10156-1-jian.j.wang@intel.com> <20180821030515.10156-3-jian.j.wang@intel.com> In-Reply-To: <20180821030515.10156-3-jian.j.wang@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2 2/4] UefiCpuPkg/CpuExceptionHandlerLib: Setup single step in #PF handler X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Aug 2018 01:15:00 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong > -----Original Message----- > From: Wang, Jian J > Sent: Tuesday, August 21, 2018 11:05 AM > To: edk2-devel@lists.01.org > Cc: Dong, Eric ; Laszlo Ersek ; N= i, > Ruiyu > Subject: [PATCH v2 2/4] UefiCpuPkg/CpuExceptionHandlerLib: Setup single > step in #PF handler >=20 > > v2 changes: > > n/a >=20 > Once the #PF handler has set the page to be 'present', there should be a = way > to reset it to 'not-present'. 'TF' bit in EFLAGS can be used for this pur= pose. 'TF' > bit will be set in interrupted function context so that it can be trigger= ed once > the cpu control returns back to the instruction causing #PF and re-execut= e it. >=20 > This is an necessary step to implement non-stop mode for Heap Guard and > NULL Pointer Detection feature. >=20 > Cc: Eric Dong > Cc: Laszlo Ersek > Cc: Ruiyu Ni > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Jian J Wang > --- > .../Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm | 7 > +++++++ > .../Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm | 4 += -- > - > .../Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 4 > ++++ > 3 files changed, 12 insertions(+), 3 deletions(-) >=20 > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.na > sm > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.na > sm > index 45d6474091..6fcf5fb23f 100644 > --- > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.na > sm > +++ > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm > +++ .nasm > @@ -383,6 +383,13 @@ ErrorCodeAndVectorOnStack: > pop dword [ebp - 4] > mov esp, ebp > pop ebp > + > +; Enable TF bit after page fault handler runs > + cmp dword [esp], 14 ; #PF? > + jne .5 > + bts dword [esp + 16], 8 ; EFLAGS > + > +.5: > add esp, 8 > cmp dword [esp - 16], 0 ; check > EXCEPTION_HANDLER_CONTEXT.OldIdtHandler > jz DoReturn > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.n > asm > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.n > asm > index 62bcedea1a..7aac29c7e7 100644 > --- > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.n > asm > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAs > +++ m.nasm > @@ -355,10 +355,8 @@ o16 mov [ecx + IA32_TSS._SS], ax > movzx ebx, word [ecx + IA32_TSS._CS] > mov [eax - 0x8], ebx ; create CS in old stac= k > mov ebx, dword [ecx + IA32_TSS.EFLAGS] > - bts ebx, 8 > + bts ebx, 8 ; Set TF > mov [eax - 0x4], ebx ; create eflags in old = stack > - mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old = TSS > - mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer > sub eax, 0xc ; minus 12 byte > mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer >=20 > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.na > sm > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.na > sm > index 7b97810d10..f842af2336 100644 > --- > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.na > sm > +++ > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm. > +++ nasm > @@ -336,6 +336,10 @@ HasErrorCode: > pop r15 >=20 > mov rsp, rbp > + cmp qword [rbp + 8], 14 ; #PF? > + jne .1 > + bts qword [rsp + 40], 8 ; RFLAGS.TF > +.1: > pop rbp > add rsp, 16 > cmp qword [rsp - 32], 0 ; check > EXCEPTION_HANDLER_CONTEXT.OldIdtHandler > -- > 2.16.2.windows.1