From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B1A9121140F47 for ; Tue, 25 Sep 2018 01:14:50 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Sep 2018 01:14:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,301,1534834800"; d="scan'208";a="94582558" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga002.jf.intel.com with ESMTP; 25 Sep 2018 01:14:43 -0700 Received: from fmsmsx101.amr.corp.intel.com (10.18.124.199) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 25 Sep 2018 01:14:43 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx101.amr.corp.intel.com (10.18.124.199) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 25 Sep 2018 01:14:42 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.140]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.183]) with mapi id 14.03.0319.002; Tue, 25 Sep 2018 16:14:41 +0800 From: "Dong, Eric" To: "Ni, Ruiyu" , "edk2-devel@lists.01.org" CC: "Kinney, Michael D" Thread-Topic: [edk2] [PATCH] UefiCpuPkg/MtrrLib: Revert "Skip MSR access when the pair is invalid" Thread-Index: AQHUVI+eu1vltM+MhEqq0hUS8GiDu6UApl8g Date: Tue, 25 Sep 2018 08:14:40 +0000 Message-ID: References: <20180925052213.12764-1-ruiyu.ni@intel.com> In-Reply-To: <20180925052213.12764-1-ruiyu.ni@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg/MtrrLib: Revert "Skip MSR access when the pair is invalid" X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Sep 2018 08:14:50 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Ruiyu Ni > Sent: Tuesday, September 25, 2018 1:22 PM > To: edk2-devel@lists.01.org > Cc: Kinney, Michael D ; Dong, Eric > > Subject: [edk2] [PATCH] UefiCpuPkg/MtrrLib: Revert "Skip MSR access when > the pair is invalid" >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1187 >=20 > The patch reverts 9c8c4478cfcacaf5fd60b75ff78d26732d93a5b8 > "UefiCpuPkg/MtrrLib: Skip Base MSR access when the pair is invalid". >=20 > Microsoft Windows will report an error in event manager if MTRR usage is > different across hibernate even when the difference is in an non valid MT= RR > pair. This seems like a bug in Windows but for compatibility and servicin= g > reasons we think a change in UEFI would wise. > A Windows change has already been submitted for the next iteration > (2019 time frame). >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ruiyu Ni > Cc: Michael D Kinney > Cc: Eric Dong > Cc: Sean Brogan > --- > UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 29 +++++++++++++---------------- > 1 file changed, 13 insertions(+), 16 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c > b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c > index dfce9a996b..086f7ad8f0 100644 > --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c > +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c > @@ -449,13 +449,10 @@ MtrrGetVariableMtrrWorker ( >=20 > for (Index =3D 0; Index < VariableMtrrCount; Index++) { > if (MtrrSetting =3D=3D NULL) { > - VariableSettings->Mtrr[Index].Mask =3D AsmReadMsr64 > (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1)); > - // > - // Skip to read the Base MSR when the Mask.V is not set. > - // > - if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings- > >Mtrr[Index].Mask)->Bits.V !=3D 0) { > - VariableSettings->Mtrr[Index].Base =3D AsmReadMsr64 > (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1)); > - } > + VariableSettings->Mtrr[Index].Base =3D > + AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1)); > + VariableSettings->Mtrr[Index].Mask =3D > + AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1)); > } else { > VariableSettings->Mtrr[Index].Base =3D MtrrSetting- > >Variables.Mtrr[Index].Base; > VariableSettings->Mtrr[Index].Mask =3D MtrrSetting- > >Variables.Mtrr[Index].Mask; > @@ -2604,14 +2601,14 @@ MtrrSetVariableMtrrWorker ( > ASSERT (VariableMtrrCount <=3D ARRAY_SIZE (VariableSettings->Mtrr)); >=20 > for (Index =3D 0; Index < VariableMtrrCount; Index++) { > - // > - // Mask MSR is always updated since caller might need to invalidate = the > MSR pair. > - // Base MSR is skipped when Mask.V is not set. > - // > - AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), > VariableSettings->Mtrr[Index].Mask); > - if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings- > >Mtrr[Index].Mask)->Bits.V !=3D 0) { > - AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), > VariableSettings->Mtrr[Index].Base); > - } > + AsmWriteMsr64 ( > + MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), > + VariableSettings->Mtrr[Index].Base > + ); > + AsmWriteMsr64 ( > + MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), > + VariableSettings->Mtrr[Index].Mask > + ); > } > } >=20 > @@ -2868,7 +2865,7 @@ MtrrDebugPrintAllMtrrsWorker ( > } > ContainVariableMtrr =3D FALSE; > for (Index =3D 0; Index < VariableMtrrCount; Index++) { > - if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&Mtrrs- > >Variables.Mtrr[Index].Mask)->Bits.V =3D=3D 0) { > + if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) =3D=3D 0) { > // > // If mask is not valid, then do not display range > // > -- > 2.16.1.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel