From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A0AD8211575DC for ; Tue, 25 Sep 2018 17:51:40 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Sep 2018 17:51:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,304,1534834800"; d="scan'208";a="265725730" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga005.fm.intel.com with ESMTP; 25 Sep 2018 17:46:07 -0700 Received: from fmsmsx123.amr.corp.intel.com (10.18.125.38) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 25 Sep 2018 17:46:07 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx123.amr.corp.intel.com (10.18.125.38) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 25 Sep 2018 17:46:07 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.140]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.245]) with mapi id 14.03.0319.002; Wed, 26 Sep 2018 08:46:05 +0800 From: "Dong, Eric" To: "Wu, Hao A" , "edk2-devel@lists.01.org" CC: Laszlo Ersek , "Yao, Jiewen" , "Kinney, Michael D" Thread-Topic: [PATCH v2 5/5] UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5753] Fix bounds check bypass Thread-Index: AQHUVJbYkhIMo1iB5kiUwz4uSb6bPKUBu1OA Date: Wed, 26 Sep 2018 00:46:04 +0000 Message-ID: References: <20180925061259.31680-1-hao.a.wu@intel.com> <20180925061259.31680-6-hao.a.wu@intel.com> In-Reply-To: <20180925061259.31680-6-hao.a.wu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2 5/5] UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5753] Fix bounds check bypass X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Sep 2018 00:51:40 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong > -----Original Message----- > From: Wu, Hao A > Sent: Tuesday, September 25, 2018 2:13 PM > To: edk2-devel@lists.01.org > Cc: Wu, Hao A ; Laszlo Ersek ; > Yao, Jiewen ; Kinney, Michael D > ; Dong, Eric > Subject: [PATCH v2 5/5] UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5753] > Fix bounds check bypass >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D1194 >=20 > Speculative execution is used by processor to avoid having to wait for > data to arrive from memory, or for previous operations to finish, the > processor may speculate as to what will be executed. >=20 > If the speculation is incorrect, the speculatively executed instructions > might leave hints such as which memory locations have been brought into > cache. Malicious actors can use the bounds check bypass method (code > gadgets with controlled external inputs) to infer data values that have > been used in speculative operations to reveal secrets which should not > otherwise be accessed. >=20 > It is possible for SMI handler(s) to call EFI_SMM_CPU_PROTOCOL service > ReadSaveState() and use the content in the 'CommBuffer' (controlled > external inputs) as the 'CpuIndex'. So this commit will insert AsmLfence > API to mitigate the bounds check bypass issue within SmmReadSaveState(). >=20 > For SmmReadSaveState(): >=20 > The 'CpuIndex' will be passed into function ReadSaveStateRegister(). And > then in to ReadSaveStateRegisterByIndex(). >=20 > With the call: > ReadSaveStateRegisterByIndex ( > CpuIndex, > SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, > sizeof(IoMisc.Uint32), > &IoMisc.Uint32 > ); >=20 > The 'IoMisc' can be a cross boundary access during speculative execution. > Later, 'IoMisc' is used as the index to access buffers 'mSmmCpuIoWidth' > and 'mSmmCpuIoType'. One can observe which part of the content within > those buffers was brought into cache to possibly reveal the value of > 'IoMisc'. >=20 > Hence, this commit adds a AsmLfence() after the check of 'CpuIndex' > within function SmmReadSaveState() to prevent the speculative execution. >=20 > A more detailed explanation of the purpose of commit is under the > 'Bounds check bypass mitigation' section of the below link: > https://software.intel.com/security-software-guidance/insights/host- > firmware-speculative-execution-side-channel-mitigation >=20 > And the document at: > https://software.intel.com/security-software-guidance/api- > app/sites/default/files/337879-analyzing-potential-bounds-Check-bypass- > vulnerabilities.pdf >=20 > Cc: Laszlo Ersek > Cc: Jiewen Yao > Cc: Michael D Kinney > Cc: Eric Dong > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Hao Wu >=20 > cb pismm > --- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 5 +++++ > 1 file changed, 5 insertions(+) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c > index fbf74e8d90..19979d5418 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c > @@ -237,6 +237,11 @@ SmmReadSaveState ( > if ((CpuIndex >=3D gSmst->NumberOfCpus) || (Buffer =3D=3D NULL)) { > return EFI_INVALID_PARAMETER; > } > + // > + // The AsmLfence() call here is to ensure the above check for the > CpuIndex > + // has been completed before the execution of subsequent codes. > + // > + AsmLfence (); >=20 > // > // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID > -- > 2.12.0.windows.1