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* [Patch] UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table.
@ 2018-10-09  1:51 Eric Dong
  2018-10-09  1:59 ` Wang, Jian J
  2018-10-09  2:05 ` Dong, Eric
  0 siblings, 2 replies; 16+ messages in thread
From: Eric Dong @ 2018-10-09  1:51 UTC (permalink / raw)
  To: edk2-devel; +Cc: Ruiyu Ni, Laszlo Ersek, Jian J Wang

PEI Stack Guard needs to enable paging. This might cause #GP in the
transition from 32-bit PEI to 64-bit SMM due to the code trying to
write CR3 register with PML4 page table while the processor is enabled
with PAE paging.

Simply disabling paging before updating CR3 can solve this conflict.

Change-Id: I99bfdba5daa48a95a4c4ef97eeca1af086558957
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by:Eric Dong <eric.dong@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
 UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c       | 7 +++++++
 UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf | 1 +
 2 files changed, 8 insertions(+)

diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
index f164c1713b..b3bf56e13d 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
@@ -1105,6 +1105,13 @@ S3RestoreConfig2 (
       //
       SetInterruptState (InterruptStatus);
 
+      if (PcdGetBool (PcdCpuStackGuard)) {
+        //
+        // Paging already been enabled, to avoid conflict configuration,
+        // disable paging first anyway.
+        //
+        AsmWriteCr0 (AsmReadCr0 () & (~BIT31));
+      }
       AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3);
 
       //
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
index 6ce1bf944c..0f131d19df 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
@@ -90,6 +90,7 @@
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable  ## SOMETIMES_CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask    ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard                       ## CONSUMES
 
 [Depex]
   TRUE
-- 
2.15.0.windows.1



^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [Patch] UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table.
@ 2018-10-10  7:43 Eric Dong
  2018-10-10  7:58 ` Yao, Jiewen
  0 siblings, 1 reply; 16+ messages in thread
From: Eric Dong @ 2018-10-10  7:43 UTC (permalink / raw)
  To: edk2-devel; +Cc: Ruiyu Ni, Laszlo Ersek, Jian J Wang

V4:
Only disable paging when it is enabled.

V3 changes:
No need to change inf file.

V2 changes:
Only disable paging in 32 bit mode, no matter it is enable or not.

V1 changes:
PEI Stack Guard needs to enable paging. This might cause #GP if code
trying to write CR3 register with PML4 page table while the processor
is enabled with PAE paging.

Simply disabling paging before updating CR3 can solve this conflict.

It's an regression caused by change: 0a0d5296e448fc350de1594c49b9c0deff7fad60

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1232

Change-Id: I99bfdba5daa48a95a4c4ef97eeca1af086558957
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by:Eric Dong <eric.dong@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
 UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
index f164c1713b..c059c42db5 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
@@ -964,6 +964,7 @@ S3RestoreConfig2 (
   VOID                                          *GuidHob;
   BOOLEAN                                       Build4GPageTableOnly;
   BOOLEAN                                       InterruptStatus;
+  IA32_CR0                                      CR0Reg;
 
   TempAcpiS3Context = 0;
   TempEfiBootScriptExecutorVariable = 0;
@@ -1105,6 +1106,17 @@ S3RestoreConfig2 (
       //
       SetInterruptState (InterruptStatus);
 
+      if (sizeof (UINTN) == sizeof (UINT32)) {
+        CR0Reg.UintN = AsmReadCr0 ();
+        if (CR0Reg.Bits.PG != 0) {
+          //
+          // We're in 32-bit mode, with paging enabled. We can't set CR3 to
+          // the 64-bit page tables without first disabling paging.
+          //
+          CR0Reg.Bits.PG = 0;
+          AsmWriteCr0 (CR0Reg.UintN);
+        }
+      }
       AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3);
 
       //
-- 
2.15.0.windows.1



^ permalink raw reply related	[flat|nested] 16+ messages in thread
end of thread, other threads:[~2018-10-10 14:00 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-10-09  1:51 [Patch] UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table Eric Dong
2018-10-09  1:59 ` Wang, Jian J
2018-10-09  2:03   ` Wang, Jian J
2018-10-09  2:27     ` Dong, Eric
2018-10-09  2:05 ` Dong, Eric
2018-10-09  2:15   ` Ni, Ruiyu
2018-10-09  8:09     ` Laszlo Ersek
2018-10-09  8:26       ` Ni, Ruiyu
2018-10-09  8:54         ` Laszlo Ersek
  -- strict thread matches above, loose matches on Subject: below --
2018-10-10  7:43 Eric Dong
2018-10-10  7:58 ` Yao, Jiewen
2018-10-10 13:03   ` Laszlo Ersek
2018-10-10 13:14     ` Yao, Jiewen
2018-10-10 13:19       ` Laszlo Ersek
2018-10-10 13:30         ` Yao, Jiewen
2018-10-10 14:00           ` Laszlo Ersek

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