Re: [PATCH] UefiCpuPkg/CpuExceptionHandlerLib: always clear descriptor data in advance

["Dong, Eric" <eric.dong@intel.com>]

Reviewed-by: Eric Dong <eric.dong@intel.com>

> -----Original Message-----
> From: Wang, Jian J
> Sent: Wednesday, October 17, 2018 4:35 PM
> To: edk2-devel@lists.01.org
> Cc: Dong, Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>; Ni,
> Ruiyu <ruiyu.ni@intel.com>
> Subject: [PATCH] UefiCpuPkg/CpuExceptionHandlerLib: always clear
> descriptor data in advance
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1237
> 
> Sometimes the memory will be contaminated by random data left in last
> boot (warm reset). The code should not assume the allocated memory is
> always filled with zero. This patch add code to clear data structure used for
> stack switch to prevent such problem from happening.
> 
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> ---
>  UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c |
> 3 +++
> UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c  |
> 3 +++
>  2 files changed, 6 insertions(+)
> 
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.
> c
> index 031d0d35fa..eebd27a25d 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandle
> +++ r.c
> @@ -214,6 +214,7 @@ ArchSetupExcpetionStack (
>    //
>    TssBase = (UINTN)Tss;
> 
> +  TssDesc->Uint64          = 0;
>    TssDesc->Bits.LimitLow   = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
>    TssDesc->Bits.BaseLow    = (UINT16)TssBase;
>    TssDesc->Bits.BaseMid    = (UINT8)(TssBase >> 16);
> @@ -238,6 +239,7 @@ ArchSetupExcpetionStack (
>      //
>      TssBase = (UINTN)Tss;
> 
> +    TssDesc->Uint64         = 0;
>      TssDesc->Bits.LimitLow  = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
>      TssDesc->Bits.BaseLow   = (UINT16)TssBase;
>      TssDesc->Bits.BaseMid   = (UINT8)(TssBase >> 16);
> @@ -255,6 +257,7 @@ ArchSetupExcpetionStack (
>        continue;
>      }
> 
> +    SetMem (Tss, sizeof (IA32_TASK_STATE_SEGMENT), 0);
>      Tss->EIP    = (UINT32)(TemplateMap.ExceptionStart
>                             + Vector * TemplateMap.ExceptionStubHeaderSize);
>      Tss->EFLAGS = 0x2;
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> index 93ecf5ae5a..6745bc77c0 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler
> +++ .c
> @@ -219,6 +219,8 @@ ArchSetupExcpetionStack (
>    //
>    TssBase = (UINTN)Tss;
> 
> +  TssDesc->Uint128.Uint64  = 0;
> +  TssDesc->Uint128.Uint64_1= 0;
>    TssDesc->Bits.LimitLow   = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
>    TssDesc->Bits.BaseLow    = (UINT16)TssBase;
>    TssDesc->Bits.BaseMidl   = (UINT8)(TssBase >> 16);
> @@ -231,6 +233,7 @@ ArchSetupExcpetionStack (
>    //
>    // Fixup exception task descriptor and task-state segment
>    //
> +  SetMem (Tss, sizeof (IA32_TASK_STATE_SEGMENT), 0);
>    StackTop = StackSwitchData->X64.KnownGoodStackTop -
> CPU_STACK_ALIGNMENT;
>    StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
>    IdtTable = StackSwitchData->X64.IdtTable;
> --
> 2.16.2.windows.1