From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3B10A2194D387 for ; Wed, 17 Oct 2018 17:54:28 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Oct 2018 17:54:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,393,1534834800"; d="scan'208";a="100377864" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga001.jf.intel.com with ESMTP; 17 Oct 2018 17:54:27 -0700 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 17 Oct 2018 17:54:27 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 17 Oct 2018 17:54:26 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.217]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.183]) with mapi id 14.03.0319.002; Thu, 18 Oct 2018 08:53:17 +0800 From: "Dong, Eric" To: "Wang, Jian J" , "edk2-devel@lists.01.org" CC: Laszlo Ersek , "Ni, Ruiyu" Thread-Topic: [PATCH] UefiCpuPkg/CpuExceptionHandlerLib: always clear descriptor data in advance Thread-Index: AQHUZfRXj2ajpQmMd0aoDpzYJ+7BAKUkLd+g Date: Thu, 18 Oct 2018 00:53:16 +0000 Message-ID: References: <20181017083448.3436-1-jian.j.wang@intel.com> In-Reply-To: <20181017083448.3436-1-jian.j.wang@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg/CpuExceptionHandlerLib: always clear descriptor data in advance X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 Oct 2018 00:54:28 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong > -----Original Message----- > From: Wang, Jian J > Sent: Wednesday, October 17, 2018 4:35 PM > To: edk2-devel@lists.01.org > Cc: Dong, Eric ; Laszlo Ersek ; N= i, > Ruiyu > Subject: [PATCH] UefiCpuPkg/CpuExceptionHandlerLib: always clear > descriptor data in advance >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1237 >=20 > Sometimes the memory will be contaminated by random data left in last > boot (warm reset). The code should not assume the allocated memory is > always filled with zero. This patch add code to clear data structure used= for > stack switch to prevent such problem from happening. >=20 > Cc: Eric Dong > Cc: Laszlo Ersek > Cc: Ruiyu Ni > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Jian J Wang > --- > UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c | > 3 +++ > UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c | > 3 +++ > 2 files changed, 6 insertions(+) >=20 > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler. > c > index 031d0d35fa..eebd27a25d 100644 > --- > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c > +++ > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandle > +++ r.c > @@ -214,6 +214,7 @@ ArchSetupExcpetionStack ( > // > TssBase =3D (UINTN)Tss; >=20 > + TssDesc->Uint64 =3D 0; > TssDesc->Bits.LimitLow =3D sizeof(IA32_TASK_STATE_SEGMENT) - 1; > TssDesc->Bits.BaseLow =3D (UINT16)TssBase; > TssDesc->Bits.BaseMid =3D (UINT8)(TssBase >> 16); > @@ -238,6 +239,7 @@ ArchSetupExcpetionStack ( > // > TssBase =3D (UINTN)Tss; >=20 > + TssDesc->Uint64 =3D 0; > TssDesc->Bits.LimitLow =3D sizeof(IA32_TASK_STATE_SEGMENT) - 1; > TssDesc->Bits.BaseLow =3D (UINT16)TssBase; > TssDesc->Bits.BaseMid =3D (UINT8)(TssBase >> 16); > @@ -255,6 +257,7 @@ ArchSetupExcpetionStack ( > continue; > } >=20 > + SetMem (Tss, sizeof (IA32_TASK_STATE_SEGMENT), 0); > Tss->EIP =3D (UINT32)(TemplateMap.ExceptionStart > + Vector * TemplateMap.ExceptionStubHeaderSiz= e); > Tss->EFLAGS =3D 0x2; > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c > index 93ecf5ae5a..6745bc77c0 100644 > --- > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c > +++ > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler > +++ .c > @@ -219,6 +219,8 @@ ArchSetupExcpetionStack ( > // > TssBase =3D (UINTN)Tss; >=20 > + TssDesc->Uint128.Uint64 =3D 0; > + TssDesc->Uint128.Uint64_1=3D 0; > TssDesc->Bits.LimitLow =3D sizeof(IA32_TASK_STATE_SEGMENT) - 1; > TssDesc->Bits.BaseLow =3D (UINT16)TssBase; > TssDesc->Bits.BaseMidl =3D (UINT8)(TssBase >> 16); > @@ -231,6 +233,7 @@ ArchSetupExcpetionStack ( > // > // Fixup exception task descriptor and task-state segment > // > + SetMem (Tss, sizeof (IA32_TASK_STATE_SEGMENT), 0); > StackTop =3D StackSwitchData->X64.KnownGoodStackTop - > CPU_STACK_ALIGNMENT; > StackTop =3D (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT); > IdtTable =3D StackSwitchData->X64.IdtTable; > -- > 2.16.2.windows.1