From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 61EC92117D758 for ; Mon, 29 Oct 2018 19:30:19 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Oct 2018 19:30:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,442,1534834800"; d="scan'208";a="96119365" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga003.jf.intel.com with ESMTP; 29 Oct 2018 19:30:18 -0700 Received: from fmsmsx101.amr.corp.intel.com (10.18.124.199) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 29 Oct 2018 19:30:17 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx101.amr.corp.intel.com (10.18.124.199) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 29 Oct 2018 19:30:17 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.84]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.214]) with mapi id 14.03.0415.000; Tue, 30 Oct 2018 10:30:11 +0800 From: "Dong, Eric" To: =?iso-8859-1?Q?Marvin_H=E4user?= , "edk2-devel@lists.01.org" CC: "lersek@redhat.com" Thread-Topic: [PATCH 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Fix ASSERT for success. Thread-Index: AQHUbptnvLzQubnneUOFpUp6QQY5eKU3EwHg Date: Tue, 30 Oct 2018 02:30:11 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Fix ASSERT for success. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 30 Oct 2018 02:30:19 -0000 Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi Marvin, Thanks for your contribution. I have reviewed them and pushed to trunk. SHA numbers are:=20 SHA-1: 4222e8e7e421e9c8d2c2f319a3860dd3332d6255 SHA-1: 37fba7c2762e114a280e3b361b53ded034aac7e3 One more question which just curious by me, how you find this issue? by too= l or code review? Thanks, Eric > -----Original Message----- > From: Marvin H=E4user [mailto:Marvin.Haeuser@outlook.com] > Sent: Sunday, October 28, 2018 4:51 PM > To: edk2-devel@lists.01.org > Cc: Dong, Eric ; lersek@redhat.com > Subject: [PATCH 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Fix ASSERT for > success. >=20 > Index is initialized to MAX_UINT16 as default failure value, which is wha= t the > ASSERT is supposed to test for. The ASSERT condition however can never > return FALSE for INT16 !=3D int, as due to Integer Promotion[1], Index is > converted to int, which can never result in -1. >=20 > Furthermore, Index is used as a for loop index variable inbetween its > initialization and the ASSERT, so the value is unconditionally overwritte= n too. >=20 > Fix the ASSERT check to compare Index to its upper boundary, which it wil= l be > equal to if the loop was not broken out of on success. >=20 > [1] ISO/IEC 9899:2011, 6.5.9.4 >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marvin Haeuser > --- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c > index b7c3ad31e82c..89b3f2b7257f 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c > @@ -110,7 +110,6 @@ GetProtectedModeCS ( > UINTN GdtEntryCount; > UINT16 Index; >=20 > - Index =3D (UINT16) -1; > AsmReadGdtr (&GdtrDesc); > GdtEntryCount =3D (GdtrDesc.Limit + 1) / sizeof > (IA32_SEGMENT_DESCRIPTOR); > GdtEntry =3D (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; @@ -122,7 > +121,7 @@ GetProtectedModeCS ( > } > GdtEntry++; > } > - ASSERT (Index !=3D -1); > + ASSERT (Index !=3D GdtEntryCount); > return Index * 8; > } >=20 > -- > 2.19.1.windows.1