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 Mon, 8 Apr 2019 16:00:09 +0800
From: "Dong, Eric" <eric.dong@intel.com>
To: "Ni, Ray" <ray.ni@intel.com>, "devel@edk2.groups.io"
	<devel@edk2.groups.io>
Subject: Re: [PATCH] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging
Thread-Topic: [PATCH] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for
 5-level paging
Thread-Index: AQHU7dzb9xrMI6/X0k+weHgwdB5c/6Yx5diQ
Date: Mon, 8 Apr 2019 08:00:08 +0000
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References: <20190408073240.89024-1-ray.ni@intel.com>
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Hi Ray,

Please use new Reserved7 for the reserved field because Reserve6 bit width =
has change.

Thanks,
Eric
> -----Original Message-----
> From: Ni, Ray
> Sent: Monday, April 8, 2019 3:33 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric <eric.dong@intel.com>
> Subject: [PATCH] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-
> level paging
>=20
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ray Ni <ray.ni@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> ---
>  UefiCpuPkg/Include/Register/Cpuid.h | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>=20
> diff --git a/UefiCpuPkg/Include/Register/Cpuid.h
> b/UefiCpuPkg/Include/Register/Cpuid.h
> index e0f4f968f4..0e8fd17b78 100644
> --- a/UefiCpuPkg/Include/Register/Cpuid.h
> +++ b/UefiCpuPkg/Include/Register/Cpuid.h
> @@ -1506,8 +1506,11 @@ typedef union {
>      /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
>      ///
>      UINT32  AVX512_VPOPCNTDQ:1;
> -    UINT32  Reserved6:2;
> -
> +    UINT32  Reserved6:1;
> +    ///
> +    /// [Bits 16] Supports 5-level paging if 1.
> +    ///
> +    UINT32  FiveLevelPage:1;
>      ///
>      /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX
> instructions
>      /// in 64-bit mode.
> --
> 2.21.0.windows.1