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 Tue, 9 Apr 2019 08:10:58 +0800
From: "Dong, Eric" <eric.dong@intel.com>
To: "Ni, Ray" <ray.ni@intel.com>, "devel@edk2.groups.io"
	<devel@edk2.groups.io>
Subject: Re: [PATCH v2] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging
Thread-Topic: [PATCH v2] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure
 for 5-level paging
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Date: Tue, 9 Apr 2019 00:10:57 +0000
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Reviewed-by: Eric Dong <eric.dong@intel.com>

> -----Original Message-----
> From: Ni, Ray
> Sent: Monday, April 8, 2019 5:11 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric <eric.dong@intel.com>
> Subject: [PATCH v2] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure
> for 5-level paging
>=20
> Reserved6 is changed to Reserved7 because the bit width is changed.
>=20
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ray Ni <ray.ni@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> ---
>  UefiCpuPkg/Include/Register/Cpuid.h | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>=20
> diff --git a/UefiCpuPkg/Include/Register/Cpuid.h
> b/UefiCpuPkg/Include/Register/Cpuid.h
> index e0f4f968f4..a67f2a1dff 100644
> --- a/UefiCpuPkg/Include/Register/Cpuid.h
> +++ b/UefiCpuPkg/Include/Register/Cpuid.h
> @@ -1506,8 +1506,11 @@ typedef union {
>      /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
>      ///
>      UINT32  AVX512_VPOPCNTDQ:1;
> -    UINT32  Reserved6:2;
> -
> +    UINT32  Reserved7:1;
> +    ///
> +    /// [Bits 16] Supports 5-level paging if 1.
> +    ///
> +    UINT32  FiveLevelPage:1;
>      ///
>      /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX
> instructions
>      /// in 64-bit mode.
> --
> 2.21.0.windows.1