* [PATCH v2] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging
@ 2019-04-08 9:11 Ni, Ray
2019-04-09 0:10 ` Dong, Eric
0 siblings, 1 reply; 2+ messages in thread
From: Ni, Ray @ 2019-04-08 9:11 UTC (permalink / raw)
To: devel; +Cc: Eric Dong
Reserved6 is changed to Reserved7 because the bit width is changed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/Cpuid.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Cpuid.h b/UefiCpuPkg/Include/Register/Cpuid.h
index e0f4f968f4..a67f2a1dff 100644
--- a/UefiCpuPkg/Include/Register/Cpuid.h
+++ b/UefiCpuPkg/Include/Register/Cpuid.h
@@ -1506,8 +1506,11 @@ typedef union {
/// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
///
UINT32 AVX512_VPOPCNTDQ:1;
- UINT32 Reserved6:2;
-
+ UINT32 Reserved7:1;
+ ///
+ /// [Bits 16] Supports 5-level paging if 1.
+ ///
+ UINT32 FiveLevelPage:1;
///
/// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
/// in 64-bit mode.
--
2.21.0.windows.1
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH v2] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging
2019-04-08 9:11 [PATCH v2] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging Ni, Ray
@ 2019-04-09 0:10 ` Dong, Eric
0 siblings, 0 replies; 2+ messages in thread
From: Dong, Eric @ 2019-04-09 0:10 UTC (permalink / raw)
To: Ni, Ray, devel@edk2.groups.io
Reviewed-by: Eric Dong <eric.dong@intel.com>
> -----Original Message-----
> From: Ni, Ray
> Sent: Monday, April 8, 2019 5:11 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric <eric.dong@intel.com>
> Subject: [PATCH v2] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure
> for 5-level paging
>
> Reserved6 is changed to Reserved7 because the bit width is changed.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ray Ni <ray.ni@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> ---
> UefiCpuPkg/Include/Register/Cpuid.h | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/UefiCpuPkg/Include/Register/Cpuid.h
> b/UefiCpuPkg/Include/Register/Cpuid.h
> index e0f4f968f4..a67f2a1dff 100644
> --- a/UefiCpuPkg/Include/Register/Cpuid.h
> +++ b/UefiCpuPkg/Include/Register/Cpuid.h
> @@ -1506,8 +1506,11 @@ typedef union {
> /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
> ///
> UINT32 AVX512_VPOPCNTDQ:1;
> - UINT32 Reserved6:2;
> -
> + UINT32 Reserved7:1;
> + ///
> + /// [Bits 16] Supports 5-level paging if 1.
> + ///
> + UINT32 FiveLevelPage:1;
> ///
> /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX
> instructions
> /// in 64-bit mode.
> --
> 2.21.0.windows.1
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2019-04-09 0:11 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-04-08 9:11 [PATCH v2] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging Ni, Ray
2019-04-09 0:10 ` Dong, Eric
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox