From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: eric.dong@intel.com) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by groups.io with SMTP; Thu, 23 May 2019 16:34:18 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 May 2019 16:34:17 -0700 X-ExtLoop1: 1 Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga008.jf.intel.com with ESMTP; 23 May 2019 16:34:17 -0700 Received: from fmsmsx157.amr.corp.intel.com (10.18.116.73) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 23 May 2019 16:34:16 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX157.amr.corp.intel.com (10.18.116.73) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 23 May 2019 16:34:16 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.249]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.18]) with mapi id 14.03.0415.000; Fri, 24 May 2019 07:34:03 +0800 From: "Dong, Eric" To: "Zeng, Star" , "devel@edk2.groups.io" CC: Laszlo Ersek , "Ni, Ray" , "Kumar, Chandana C" , "Li, Kevin Y" Subject: Re: [PATCH V2] UefiCpuPkg CpuCommFeaturesLib: Fix ASSERT if LMCE is supported Thread-Topic: [PATCH V2] UefiCpuPkg CpuCommFeaturesLib: Fix ASSERT if LMCE is supported Thread-Index: AQHVEIegTpbJNwcWO0yboSPLUoPXY6Z5XuHQ Date: Thu, 23 May 2019 23:34:03 +0000 Message-ID: References: <20190522101751.89952-1-star.zeng@intel.com> In-Reply-To: <20190522101751.89952-1-star.zeng@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: eric.dong@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong > -----Original Message----- > From: Zeng, Star > Sent: Wednesday, May 22, 2019 6:18 PM > To: devel@edk2.groups.io > Cc: Zeng, Star ; Laszlo Ersek ; > Dong, Eric ; Ni, Ray ; Kumar, > Chandana C ; Li, Kevin Y > > Subject: [PATCH V2] UefiCpuPkg CpuCommFeaturesLib: Fix ASSERT if LMCE is > supported >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1829 >=20 > There will be ASSERT if LMCE is supported as below. > DXE_ASSERT!: [CpuFeaturesDxe] > XXX\UefiCpuPkg\Library\CpuCommonFeaturesLib\MachineCheck.c (342): > ConfigData !=3D ((void *) 0) >=20 > The code should get Config Data and FeatureControlGetConfigData > could be used. >=20 > This issue is there since the code was added at the commit below. >=20 > Revision: 3d6275c1137c9633ce24e31522b71105367bd6a0 > Date: 2017/8/4 8:46:41 > UefiCpuPkg CpuCommonFeaturesLib: Enable LMCE feature. >=20 > The commits below are also related to move the code. >=20 > Revision: 023387144299741d727521b425ef443438aecc1f > Date: 2017/9/1 10:12:38 > UefiCpuPkg/Lmce.c Remove useless file. >=20 > Revision: 306a5bcc6b0170d28b0db10bd359817bb4b1db9f > Date: 2017/8/17 11:40:38 > UefiCpuPkg/CpuCommonFeaturesLib: Merge machine check code to same > file. >=20 > So, the code should not be tested at all on a platform > that supports LMCE. >=20 > BTW: A typo in LmceInitialize is also fixed. > The typo is introduced by the commit below. >=20 > Revision: d28daaddb3e732468e930a809d3d3943a5de9558 > Date: 2018/10/17 9:24:05 > UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info. >=20 > Cc: Laszlo Ersek > Cc: Eric Dong > Cc: Ray Ni > Cc: Chandana Kumar > Cc: Kevin Li > Signed-off-by: Star Zeng >=20 > Notes: > v2: Based on Laszlo's great feedback. > - Update Ray's name and email address to match Maintainers.txt. > - Remove "Change-Id" line that was added unintended. > - Add more code history. >=20 > --- > UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c | 2 > +- > UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git > a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c > index 738b57dc87f9..9ddc6ce9d476 100644 > --- > a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c > +++ > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c > @@ -214,7 +214,7 @@ CpuCommonFeaturesLibConstructor ( > if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) { > Status =3D RegisterCpuFeature ( > "LMCE", > - NULL, > + FeatureControlGetConfigData, > LmceSupport, > LmceInitialize, > CPU_FEATURE_LMCE, > diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c > index 9ee559130080..2528e0044ecb 100644 > --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c > +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c > @@ -322,7 +322,7 @@ LmceInitialize ( > MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; >=20 > // > - // The scope of FastStrings bit in the MSR_IA32_MISC_ENABLE is core fo= r > below processor type, only program > + // The scope of LcmeOn bit in the MSR_IA32_MISC_ENABLE is core for > below processor type, only program > // MSR_IA32_MISC_ENABLE for thread 0 in each core. > // > if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo- > >DisplayModel) || > -- > 2.21.0.windows.1