From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: eric.dong@intel.com) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by groups.io with SMTP; Mon, 08 Jul 2019 18:08:42 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Jul 2019 18:08:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,468,1557212400"; d="scan'208";a="188670880" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga004.fm.intel.com with ESMTP; 08 Jul 2019 18:08:37 -0700 Received: from fmsmsx155.amr.corp.intel.com (10.18.116.71) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 8 Jul 2019 18:08:37 -0700 Received: from shsmsx108.ccr.corp.intel.com (10.239.4.97) by FMSMSX155.amr.corp.intel.com (10.18.116.71) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 8 Jul 2019 18:08:36 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.3]) by SHSMSX108.ccr.corp.intel.com ([169.254.8.174]) with mapi id 14.03.0439.000; Tue, 9 Jul 2019 09:08:35 +0800 From: "Dong, Eric" To: "devel@edk2.groups.io" , "Ni, Ray" CC: Laszlo Ersek Subject: Re: [edk2-devel] [PATCH v2 1/3] UefiCpuPkg/PiSmmCpu: Change variable names and comments to follow SDM Thread-Topic: [edk2-devel] [PATCH v2 1/3] UefiCpuPkg/PiSmmCpu: Change variable names and comments to follow SDM Thread-Index: AQHVMWw5YcUUtbU8y0OXj2GaGdPP6KbBgriQ Date: Tue, 9 Jul 2019 01:08:35 +0000 Message-ID: References: <20190703065416.116816-1-ray.ni@intel.com> <20190703065416.116816-2-ray.ni@intel.com> In-Reply-To: <20190703065416.116816-2-ray.ni@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: eric.dong@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Ni= , > Ray > Sent: Wednesday, July 3, 2019 2:54 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Laszlo Ersek > Subject: [edk2-devel] [PATCH v2 1/3] UefiCpuPkg/PiSmmCpu: Change > variable names and comments to follow SDM >=20 > Per SDM, for IA-32e 4-KByte paging, there are four layers in the page ta= ble > structure: > 1. PML4 > 2. Page-Directory-Pointer Table (PDPT) > 3. Page-Directory (PD) > 4. Page Table (PT) >=20 > The patch changes the local variable names and comments to use "PML4", > "PDPT", "PD", "PT" to better align to terms used in SDM. >=20 > There is no functionality impact for this change. >=20 > Signed-off-by: Ray Ni > Cc: Eric Dong > Regression-tested-by: Laszlo Ersek > --- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 114 ++++++++++++--------- > ---- > 1 file changed, 57 insertions(+), 57 deletions(-) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c > index 3b2f967355..e2b6a2d9b2 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c > @@ -535,15 +535,15 @@ InitPaging ( > ) > { > UINT64 *Pml4; > - UINT64 *Pde; > - UINT64 *Pte; > + UINT64 *Pdpt; > + UINT64 *Pd; > UINT64 *Pt; > UINTN Address; > - UINTN Level1; > - UINTN Level2; > - UINTN Level3; > - UINTN Level4; > - UINTN NumberOfPdpEntries; > + UINTN Pml4Index; > + UINTN PdptIndex; > + UINTN PdIndex; > + UINTN PtIndex; > + UINTN NumberOfPdptEntries; > UINTN NumberOfPml4Entries; > UINTN SizeOfMemorySpace; > BOOLEAN Nx; > @@ -556,143 +556,143 @@ InitPaging ( > // > if (SizeOfMemorySpace <=3D 39 ) { > NumberOfPml4Entries =3D 1; > - NumberOfPdpEntries =3D (UINT32)LShiftU64 (1, (SizeOfMemorySpace - > 30)); > + NumberOfPdptEntries =3D (UINT32)LShiftU64 (1, (SizeOfMemorySpace = - > + 30)); > } else { > NumberOfPml4Entries =3D (UINT32)LShiftU64 (1, (SizeOfMemorySpace = - > 39)); > - NumberOfPdpEntries =3D 512; > + NumberOfPdptEntries =3D 512; > } > } else { > NumberOfPml4Entries =3D 1; > - NumberOfPdpEntries =3D 4; > + NumberOfPdptEntries =3D 4; > } >=20 > // > // Go through page table and change 2MB-page into 4KB-page. > // > - for (Level1 =3D 0; Level1 < NumberOfPml4Entries; Level1++) { > + for (Pml4Index =3D 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) { > if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { > - if ((Pml4[Level1] & IA32_PG_P) =3D=3D 0) { > + if ((Pml4[Pml4Index] & IA32_PG_P) =3D=3D 0) { > // > - // If Pml4 entry does not exist, skip it > + // If PML4 entry does not exist, skip it > // > continue; > } > - Pde =3D (UINT64 *)(UINTN)(Pml4[Level1] & ~mAddressEncMask & > PHYSICAL_ADDRESS_MASK); > + Pdpt =3D (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & > + PHYSICAL_ADDRESS_MASK); > } else { > - Pde =3D (UINT64*)(UINTN)mSmmProfileCr3; > + Pdpt =3D (UINT64*)(UINTN)mSmmProfileCr3; > } > - for (Level2 =3D 0; Level2 < NumberOfPdpEntries; Level2++, Pde++) { > - if ((*Pde & IA32_PG_P) =3D=3D 0) { > + for (PdptIndex =3D 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, > Pdpt++) { > + if ((*Pdpt & IA32_PG_P) =3D=3D 0) { > // > - // If PDE entry does not exist, skip it > + // If PDPT entry does not exist, skip it > // > continue; > } > - if ((*Pde & IA32_PG_PS) !=3D 0) { > + if ((*Pdpt & IA32_PG_PS) !=3D 0) { > // > // This is 1G entry, skip it > // > continue; > } > - Pte =3D (UINT64 *)(UINTN)(*Pde & ~mAddressEncMask & > PHYSICAL_ADDRESS_MASK); > - if (Pte =3D=3D 0) { > + Pd =3D (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & > PHYSICAL_ADDRESS_MASK); > + if (Pd =3D=3D 0) { > continue; > } > - for (Level3 =3D 0; Level3 < SIZE_4KB / sizeof (*Pte); Level3++, P= te++) { > - if ((*Pte & IA32_PG_P) =3D=3D 0) { > + for (PdIndex =3D 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++,= Pd++) { > + if ((*Pd & IA32_PG_P) =3D=3D 0) { > // > - // If PTE entry does not exist, skip it > + // If PD entry does not exist, skip it > // > continue; > } > - Address =3D (((Level2 << 9) + Level3) << 21); > + Address =3D (((PdptIndex << 9) + PdIndex) << 21); >=20 > // > // If it is 2M page, check IsAddressSplit() > // > - if (((*Pte & IA32_PG_PS) !=3D 0) && IsAddressSplit (Address)) { > + if (((*Pd & IA32_PG_PS) !=3D 0) && IsAddressSplit (Address)) { > // > // Based on current page table, create 4KB page table for spl= it area. > // > - ASSERT (Address =3D=3D (*Pte & PHYSICAL_ADDRESS_MASK)); > + ASSERT (Address =3D=3D (*Pd & PHYSICAL_ADDRESS_MASK)); >=20 > Pt =3D AllocatePageTableMemory (1); > ASSERT (Pt !=3D NULL); >=20 > // Split it > - for (Level4 =3D 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++)= { > - Pt[Level4] =3D Address + ((Level4 << 12) | mAddressEncMask = | > PAGE_ATTRIBUTE_BITS); > + for (PtIndex =3D 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex= ++) { > + Pt[PtIndex] =3D Address + ((PtIndex << 12) | mAddressEncMas= k > + | PAGE_ATTRIBUTE_BITS); > } // end for PT > - *Pte =3D (UINT64)(UINTN)Pt | mAddressEncMask | > PAGE_ATTRIBUTE_BITS; > + *Pd =3D (UINT64)(UINTN)Pt | mAddressEncMask | > + PAGE_ATTRIBUTE_BITS; > } // end if IsAddressSplit > - } // end for PTE > - } // end for PDE > - } > + } // end for PD > + } // end for PDPT > + } // end for PML4 >=20 > // > // Go through page table and set several page table entries to absent= or > execute-disable. > // > DEBUG ((EFI_D_INFO, "Patch page table start ...\n")); > - for (Level1 =3D 0; Level1 < NumberOfPml4Entries; Level1++) { > + for (Pml4Index =3D 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) { > if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { > - if ((Pml4[Level1] & IA32_PG_P) =3D=3D 0) { > + if ((Pml4[Pml4Index] & IA32_PG_P) =3D=3D 0) { > // > - // If Pml4 entry does not exist, skip it > + // If PML4 entry does not exist, skip it > // > continue; > } > - Pde =3D (UINT64 *)(UINTN)(Pml4[Level1] & ~mAddressEncMask & > PHYSICAL_ADDRESS_MASK); > + Pdpt =3D (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & > + PHYSICAL_ADDRESS_MASK); > } else { > - Pde =3D (UINT64*)(UINTN)mSmmProfileCr3; > + Pdpt =3D (UINT64*)(UINTN)mSmmProfileCr3; > } > - for (Level2 =3D 0; Level2 < NumberOfPdpEntries; Level2++, Pde++) { > - if ((*Pde & IA32_PG_P) =3D=3D 0) { > + for (PdptIndex =3D 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, > Pdpt++) { > + if ((*Pdpt & IA32_PG_P) =3D=3D 0) { > // > - // If PDE entry does not exist, skip it > + // If PDPT entry does not exist, skip it > // > continue; > } > - if ((*Pde & IA32_PG_PS) !=3D 0) { > + if ((*Pdpt & IA32_PG_PS) !=3D 0) { > // > // This is 1G entry, set NX bit and skip it > // > if (mXdSupported) { > - *Pde =3D *Pde | IA32_PG_NX; > + *Pdpt =3D *Pdpt | IA32_PG_NX; > } > continue; > } > - Pte =3D (UINT64 *)(UINTN)(*Pde & ~mAddressEncMask & > PHYSICAL_ADDRESS_MASK); > - if (Pte =3D=3D 0) { > + Pd =3D (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & > PHYSICAL_ADDRESS_MASK); > + if (Pd =3D=3D 0) { > continue; > } > - for (Level3 =3D 0; Level3 < SIZE_4KB / sizeof (*Pte); Level3++, P= te++) { > - if ((*Pte & IA32_PG_P) =3D=3D 0) { > + for (PdIndex =3D 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++,= Pd++) { > + if ((*Pd & IA32_PG_P) =3D=3D 0) { > // > - // If PTE entry does not exist, skip it > + // If PD entry does not exist, skip it > // > continue; > } > - Address =3D (((Level2 << 9) + Level3) << 21); > + Address =3D (((PdptIndex << 9) + PdIndex) << 21); >=20 > - if ((*Pte & IA32_PG_PS) !=3D 0) { > + if ((*Pd & IA32_PG_PS) !=3D 0) { > // 2MB page >=20 > if (!IsAddressValid (Address, &Nx)) { > // > // Patch to remove Present flag and RW flag > // > - *Pte =3D *Pte & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS); > + *Pd =3D *Pd & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS); > } > if (Nx && mXdSupported) { > - *Pte =3D *Pte | IA32_PG_NX; > + *Pd =3D *Pd | IA32_PG_NX; > } > } else { > // 4KB page > - Pt =3D (UINT64 *)(UINTN)(*Pte & ~mAddressEncMask & > PHYSICAL_ADDRESS_MASK); > + Pt =3D (UINT64 *)(UINTN)(*Pd & ~mAddressEncMask & > + PHYSICAL_ADDRESS_MASK); > if (Pt =3D=3D 0) { > continue; > } > - for (Level4 =3D 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++,= Pt++) { > + for (PtIndex =3D 0; PtIndex < SIZE_4KB / sizeof(*Pt); > + PtIndex++, Pt++) { > if (!IsAddressValid (Address, &Nx)) { > *Pt =3D *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS); > } > @@ -702,9 +702,9 @@ InitPaging ( > Address +=3D SIZE_4KB; > } // end for PT > } // end if PS > - } // end for PTE > - } // end for PDE > - } > + } // end for PD > + } // end for PDPT > + } // end for PML4 >=20 > // > // Flush TLB > -- > 2.21.0.windows.1 >=20 >=20 >=20