From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: eric.dong@intel.com) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by groups.io with SMTP; Thu, 01 Aug 2019 18:08:36 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Aug 2019 18:08:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,336,1559545200"; d="scan'208";a="178004292" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga006.jf.intel.com with ESMTP; 01 Aug 2019 18:08:35 -0700 Received: from fmsmsx152.amr.corp.intel.com (10.18.125.5) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 1 Aug 2019 18:08:35 -0700 Received: from shsmsx106.ccr.corp.intel.com (10.239.4.159) by FMSMSX152.amr.corp.intel.com (10.18.125.5) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 1 Aug 2019 18:08:35 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.19]) by SHSMSX106.ccr.corp.intel.com ([169.254.10.204]) with mapi id 14.03.0439.000; Fri, 2 Aug 2019 09:08:33 +0800 From: "Dong, Eric" To: "Ni, Ray" , "devel@edk2.groups.io" CC: Laszlo Ersek Subject: Re: [PATCH v4 1/8] UefiCpuPkg/MpInitLib: Enable 5-level paging for AP when BSP's enabled Thread-Topic: [PATCH v4 1/8] UefiCpuPkg/MpInitLib: Enable 5-level paging for AP when BSP's enabled Thread-Index: AQHVSE/HhymnCCUaxU2N5GTYHxXu5abnDN8A Date: Fri, 2 Aug 2019 01:08:33 +0000 Message-ID: References: <20190801095831.274356-1-ray.ni@intel.com> <20190801095831.274356-2-ray.ni@intel.com> In-Reply-To: <20190801095831.274356-2-ray.ni@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: eric.dong@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong > -----Original Message----- > From: Ni, Ray > Sent: Thursday, August 1, 2019 5:58 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Laszlo Ersek > Subject: [PATCH v4 1/8] UefiCpuPkg/MpInitLib: Enable 5-level paging for A= P > when BSP's enabled >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2008 >=20 > MpInitLib is the library that's responsible to wake up APs to provide MP = PPI > and Protocol services. >=20 > The patch synchronizes BSP's CR4.LA57 to each AP's CR4.LA57. > Without this change, AP may enter to GP fault when BSP's 5-level page tab= le > is set to AP during AP wakes up. >=20 > Signed-off-by: Ray Ni > Cc: Eric Dong > Cc: Laszlo Ersek > --- > UefiCpuPkg/Library/MpInitLib/MpLib.c | 13 +++++++++++++ > UefiCpuPkg/Library/MpInitLib/MpLib.h | 4 ++++ > UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc | 3 ++- > UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 14 +++++++++++++- > 4 files changed, 32 insertions(+), 2 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c > b/UefiCpuPkg/Library/MpInitLib/MpLib.c > index 572495ec36..d2f18027cd 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c > @@ -790,6 +790,7 @@ FillExchangeInfoData ( > volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo; > UINTN Size; > IA32_SEGMENT_DESCRIPTOR *Selector; > + IA32_CR4 Cr4; >=20 > ExchangeInfo =3D CpuMpData->MpCpuExchangeInfo; > ExchangeInfo->Lock =3D 0; > @@ -814,6 +815,18 @@ FillExchangeInfoData ( >=20 > ExchangeInfo->InitializeFloatingPointUnitsAddress =3D > (UINTN)InitializeFloatingPointUnits; >=20 > + // > + // We can check either CPUID(7).ECX[bit16] or check CR4.LA57[bit12] > + // to determin whether 5-Level Paging is enabled. > + // CPUID(7).ECX[bit16] shows CPU's capability, CR4.LA57[bit12] shows > + // current system setting. > + // Using latter way is simpler because it also eliminates the needs > + to // check whether platform wants to enable it. > + // > + Cr4.UintN =3D AsmReadCr4 (); > + ExchangeInfo->Enable5LevelPaging =3D (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1= ); > + DEBUG ((DEBUG_INFO, "%a: 5-Level Paging =3D %d\n", gEfiCallerBaseName, > + ExchangeInfo->Enable5LevelPaging)); > + > // > // Get the BSP's data of GDT and IDT > // > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h > b/UefiCpuPkg/Library/MpInitLib/MpLib.h > index effa235778..4b12f91d47 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h > @@ -185,6 +185,10 @@ typedef struct { > UINT16 ModeTransitionSegment; > UINT32 ModeHighMemory; > UINT16 ModeHighSegment; > + // > + // Enable5LevelPaging indicates whether 5-level paging is enabled in l= ong > mode. > + // > + BOOLEAN Enable5LevelPaging; > } MP_CPU_EXCHANGE_INFO; >=20 > #pragma pack() > diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc > b/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc > index 467f54a860..58ef369342 100644 > --- a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc > +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc > @@ -1,5 +1,5 @@ > ;-----------------------------------------------------------------------= ------- ; -; > Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
> +; Copyright (c) 2015 - 2019, Intel Corporation. All rights > +reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: > @@ -40,3 +40,4 @@ ModeTransitionMemoryLocation equ LockLocation > + 94h > ModeTransitionSegmentLocation equ LockLocation + 98h > ModeHighMemoryLocation equ LockLocation + 9Ah > ModeHighSegmentLocation equ LockLocation + 9Eh > +Enable5LevelPagingLocation equ LockLocation + 0A0h > diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > index cea90f3d4d..87f2523e85 100644 > --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > @@ -1,5 +1,5 @@ > ;-----------------------------------------------------------------------= ------- ; -; > Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
> +; Copyright (c) 2015 - 2019, Intel Corporation. All rights > +reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: > @@ -100,6 +100,18 @@ SkipEnableExecuteDisableBit: > ; > mov eax, cr4 > bts eax, 5 > + > + mov esi, Enable5LevelPagingLocation > + cmp byte [ebx + esi], 0 > + jz SkipEnable5LevelPaging > + > + ; > + ; Enable 5 Level Paging > + ; > + bts eax, 12 ; Set LA57=3D1. > + > +SkipEnable5LevelPaging: > + > mov cr4, eax >=20 > ; > -- > 2.21.0.windows.1