From: "Dong, Eric" <eric.dong@intel.com>
To: "Ni, Ray" <ray.ni@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Yao, Jiewen" <jiewen.yao@intel.com>, Laszlo Ersek <lersek@redhat.com>
Subject: Re: [PATCH v4 2/8] UefiCpuPkg/CpuDxe: Remove unnecessary macros
Date: Fri, 2 Aug 2019 01:13:00 +0000 [thread overview]
Message-ID: <ED077930C258884BBCB450DB737E662259EBA3DB@shsmsx102.ccr.corp.intel.com> (raw)
In-Reply-To: <20190801095831.274356-3-ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
> -----Original Message-----
> From: Ni, Ray
> Sent: Thursday, August 1, 2019 5:58 PM
> To: devel@edk2.groups.io
> Cc: Yao, Jiewen <jiewen.yao@intel.com>; Dong, Eric <eric.dong@intel.com>;
> Laszlo Ersek <lersek@redhat.com>
> Subject: [PATCH v4 2/8] UefiCpuPkg/CpuDxe: Remove unnecessary macros
>
> Today's code defines macros like CR0_PG, CR0_WP, CR4_PSE, CR4_PAE when
> checking whether individual bits are set in CR0 or CR4 register.
>
> The patch changes the code to use IA32_CR0 and IA32_CR4 structure defined
> in MdePkg/Include/Library/BaseLib.h so that the module local macros can be
> removed.
>
> There is no functionality impact to this change.
>
> Signed-off-by: Ray Ni <ray.ni@intel.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> ---
> UefiCpuPkg/CpuDxe/CpuPageTable.c | 43 ++++++++++++++++++------------
> --
> 1 file changed, 24 insertions(+), 19 deletions(-)
>
> diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c
> b/UefiCpuPkg/CpuDxe/CpuPageTable.c
> index c369b44f12..16a2528b55 100644
> --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c
> +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c
> @@ -1,7 +1,7 @@
> /** @file
> Page table management support.
>
> - Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights
> + reserved.<BR>
> Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent @@ -21,14 +21,6 @@
> #include "CpuDxe.h"
> #include "CpuPageTable.h"
>
> -///
> -/// Paging registers
> -///
> -#define CR0_WP BIT16
> -#define CR0_PG BIT31
> -#define CR4_PSE BIT4
> -#define CR4_PAE BIT5
> -
> ///
> /// Page Table Entry
> ///
> @@ -161,6 +153,8 @@ GetCurrentPagingContext (
> UINT32 RegEax;
> CPUID_EXTENDED_CPU_SIG_EDX RegEdx;
> MSR_IA32_EFER_REGISTER MsrEfer;
> + IA32_CR4 Cr4;
> + IA32_CR0 Cr0;
>
> //
> // Don't retrieve current paging context from processor if in SMM mode.
> @@ -172,21 +166,24 @@ GetCurrentPagingContext (
> } else {
> mPagingContext.MachineType = IMAGE_FILE_MACHINE_I386;
> }
> - if ((AsmReadCr0 () & CR0_PG) != 0) {
> +
> + Cr0.UintN = AsmReadCr0 ();
> + Cr4.UintN = AsmReadCr4 ();
> +
> + if (Cr0.Bits.PG != 0) {
> mPagingContext.ContextData.X64.PageTableBase = (AsmReadCr3 () &
> PAGING_4K_ADDRESS_MASK_64);
> } else {
> mPagingContext.ContextData.X64.PageTableBase = 0;
> }
> -
> - if ((AsmReadCr4 () & CR4_PSE) != 0) {
> + if (Cr0.Bits.WP != 0) {
> + mPagingContext.ContextData.Ia32.Attributes |=
> PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE;
> + }
> + if (Cr4.Bits.PSE != 0) {
> mPagingContext.ContextData.Ia32.Attributes |=
> PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE;
> }
> - if ((AsmReadCr4 () & CR4_PAE) != 0) {
> + if (Cr4.Bits.PAE != 0) {
> mPagingContext.ContextData.Ia32.Attributes |=
> PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE;
> }
> - if ((AsmReadCr0 () & CR0_WP) != 0) {
> - mPagingContext.ContextData.Ia32.Attributes |=
> PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE;
> - }
>
> AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
> if (RegEax >= CPUID_EXTENDED_CPU_SIG) { @@ -581,12 +578,14 @@
> IsReadOnlyPageWriteProtected (
> VOID
> )
> {
> + IA32_CR0 Cr0;
> //
> // To avoid unforseen consequences, don't touch paging settings in SMM
> mode
> // in this driver.
> //
> if (!IsInSmm ()) {
> - return ((AsmReadCr0 () & CR0_WP) != 0);
> + Cr0.UintN = AsmReadCr0 ();
> + return (BOOLEAN) (Cr0.Bits.WP != 0);
> }
> return FALSE;
> }
> @@ -599,12 +598,15 @@ DisableReadOnlyPageWriteProtect (
> VOID
> )
> {
> + IA32_CR0 Cr0;
> //
> // To avoid unforseen consequences, don't touch paging settings in SMM
> mode
> // in this driver.
> //
> if (!IsInSmm ()) {
> - AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
> + Cr0.UintN = AsmReadCr0 ();
> + Cr0.Bits.WP = 0;
> + AsmWriteCr0 (Cr0.UintN);
> }
> }
>
> @@ -616,12 +618,15 @@ EnableReadOnlyPageWriteProtect (
> VOID
> )
> {
> + IA32_CR0 Cr0;
> //
> // To avoid unforseen consequences, don't touch paging settings in SMM
> mode
> // in this driver.
> //
> if (!IsInSmm ()) {
> - AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
> + Cr0.UintN = AsmReadCr0 ();
> + Cr0.Bits.WP = 1;
> + AsmWriteCr0 (Cr0.UintN);
> }
> }
>
> --
> 2.21.0.windows.1
next prev parent reply other threads:[~2019-08-02 1:13 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-01 9:58 [PATCH v4 0/8] Support 5-level paging in DXE long mode Ni, Ray
2019-08-01 9:58 ` [PATCH v4 1/8] UefiCpuPkg/MpInitLib: Enable 5-level paging for AP when BSP's enabled Ni, Ray
2019-08-02 1:08 ` Dong, Eric
2019-08-01 9:58 ` [PATCH v4 2/8] UefiCpuPkg/CpuDxe: Remove unnecessary macros Ni, Ray
2019-08-02 1:13 ` Dong, Eric [this message]
2019-08-01 9:58 ` [PATCH v4 3/8] UefiCpuPkg/CpuDxe: Support parsing 5-level page table Ni, Ray
2019-08-02 1:20 ` Dong, Eric
2019-08-01 9:58 ` [PATCH v4 4/8] MdeModulePkg/DxeIpl: Introduce PCD PcdUse5LevelPageTable Ni, Ray
2019-08-02 1:22 ` Dong, Eric
2019-08-08 5:30 ` Wu, Hao A
2019-08-08 5:46 ` [edk2-devel] " Liming Gao
2019-08-01 9:58 ` [PATCH v4 5/8] MdePkg/Cpuid.h: Move Cpuid.h from UefiCpuPkg to MdePkg Ni, Ray
2019-08-02 1:28 ` Dong, Eric
2019-08-08 3:03 ` Liming Gao
2019-08-01 9:58 ` [PATCH v4 6/8] MdeModulePkg/DxeIpl: Create 5-level page table for long mode Ni, Ray
2019-08-02 2:23 ` Dong, Eric
2019-08-08 5:34 ` Wu, Hao A
2019-08-01 9:58 ` [PATCH v4 7/8] UefiCpuPkg|MdePkg: Move Register/ folder to MdePkg/Include/ Ni, Ray
2019-08-02 2:25 ` Dong, Eric
2019-08-08 3:06 ` Liming Gao
2019-08-01 9:58 ` [PATCH v4 8/8] UefiCpuPkg: Update code to include register definitions from MdePkg Ni, Ray
2019-08-02 2:29 ` Dong, Eric
2019-08-07 20:18 ` [edk2-devel] [PATCH v4 0/8] Support 5-level paging in DXE long mode Laszlo Ersek
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