From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: eric.dong@intel.com) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by groups.io with SMTP; Thu, 01 Aug 2019 18:13:07 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Aug 2019 18:13:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,336,1559545200"; d="scan'208";a="184429319" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga002.jf.intel.com with ESMTP; 01 Aug 2019 18:13:05 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 1 Aug 2019 18:13:03 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.19]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.139]) with mapi id 14.03.0439.000; Fri, 2 Aug 2019 09:13:01 +0800 From: "Dong, Eric" To: "Ni, Ray" , "devel@edk2.groups.io" CC: "Yao, Jiewen" , Laszlo Ersek Subject: Re: [PATCH v4 2/8] UefiCpuPkg/CpuDxe: Remove unnecessary macros Thread-Topic: [PATCH v4 2/8] UefiCpuPkg/CpuDxe: Remove unnecessary macros Thread-Index: AQHVSE/JKuJ2A7b6d06De73DEZEKjqbnDhxA Date: Fri, 2 Aug 2019 01:13:00 +0000 Message-ID: References: <20190801095831.274356-1-ray.ni@intel.com> <20190801095831.274356-3-ray.ni@intel.com> In-Reply-To: <20190801095831.274356-3-ray.ni@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: eric.dong@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong > -----Original Message----- > From: Ni, Ray > Sent: Thursday, August 1, 2019 5:58 PM > To: devel@edk2.groups.io > Cc: Yao, Jiewen ; Dong, Eric ; > Laszlo Ersek > Subject: [PATCH v4 2/8] UefiCpuPkg/CpuDxe: Remove unnecessary macros >=20 > Today's code defines macros like CR0_PG, CR0_WP, CR4_PSE, CR4_PAE when > checking whether individual bits are set in CR0 or CR4 register. >=20 > The patch changes the code to use IA32_CR0 and IA32_CR4 structure defined > in MdePkg/Include/Library/BaseLib.h so that the module local macros can b= e > removed. >=20 > There is no functionality impact to this change. >=20 > Signed-off-by: Ray Ni > Cc: Jiewen Yao > Cc: Eric Dong > Cc: Laszlo Ersek > --- > UefiCpuPkg/CpuDxe/CpuPageTable.c | 43 ++++++++++++++++++------------ > -- > 1 file changed, 24 insertions(+), 19 deletions(-) >=20 > diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c > b/UefiCpuPkg/CpuDxe/CpuPageTable.c > index c369b44f12..16a2528b55 100644 > --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c > +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c > @@ -1,7 +1,7 @@ > /** @file > Page table management support. >=20 > - Copyright (c) 2017, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights > + reserved.
> Copyright (c) 2017, AMD Incorporated. All rights reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent @@ -21,14 +21,6 @@ > #include "CpuDxe.h" > #include "CpuPageTable.h" >=20 > -/// > -/// Paging registers > -/// > -#define CR0_WP BIT16 > -#define CR0_PG BIT31 > -#define CR4_PSE BIT4 > -#define CR4_PAE BIT5 > - > /// > /// Page Table Entry > /// > @@ -161,6 +153,8 @@ GetCurrentPagingContext ( > UINT32 RegEax; > CPUID_EXTENDED_CPU_SIG_EDX RegEdx; > MSR_IA32_EFER_REGISTER MsrEfer; > + IA32_CR4 Cr4; > + IA32_CR0 Cr0; >=20 > // > // Don't retrieve current paging context from processor if in SMM mode= . > @@ -172,21 +166,24 @@ GetCurrentPagingContext ( > } else { > mPagingContext.MachineType =3D IMAGE_FILE_MACHINE_I386; > } > - if ((AsmReadCr0 () & CR0_PG) !=3D 0) { > + > + Cr0.UintN =3D AsmReadCr0 (); > + Cr4.UintN =3D AsmReadCr4 (); > + > + if (Cr0.Bits.PG !=3D 0) { > mPagingContext.ContextData.X64.PageTableBase =3D (AsmReadCr3 () & > PAGING_4K_ADDRESS_MASK_64); > } else { > mPagingContext.ContextData.X64.PageTableBase =3D 0; > } > - > - if ((AsmReadCr4 () & CR4_PSE) !=3D 0) { > + if (Cr0.Bits.WP !=3D 0) { > + mPagingContext.ContextData.Ia32.Attributes |=3D > PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE; > + } > + if (Cr4.Bits.PSE !=3D 0) { > mPagingContext.ContextData.Ia32.Attributes |=3D > PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE; > } > - if ((AsmReadCr4 () & CR4_PAE) !=3D 0) { > + if (Cr4.Bits.PAE !=3D 0) { > mPagingContext.ContextData.Ia32.Attributes |=3D > PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE; > } > - if ((AsmReadCr0 () & CR0_WP) !=3D 0) { > - mPagingContext.ContextData.Ia32.Attributes |=3D > PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE; > - } >=20 > AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); > if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) { @@ -581,12 +578,14 @@ > IsReadOnlyPageWriteProtected ( > VOID > ) > { > + IA32_CR0 Cr0; > // > // To avoid unforseen consequences, don't touch paging settings in SMM > mode > // in this driver. > // > if (!IsInSmm ()) { > - return ((AsmReadCr0 () & CR0_WP) !=3D 0); > + Cr0.UintN =3D AsmReadCr0 (); > + return (BOOLEAN) (Cr0.Bits.WP !=3D 0); > } > return FALSE; > } > @@ -599,12 +598,15 @@ DisableReadOnlyPageWriteProtect ( > VOID > ) > { > + IA32_CR0 Cr0; > // > // To avoid unforseen consequences, don't touch paging settings in SMM > mode > // in this driver. > // > if (!IsInSmm ()) { > - AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP); > + Cr0.UintN =3D AsmReadCr0 (); > + Cr0.Bits.WP =3D 0; > + AsmWriteCr0 (Cr0.UintN); > } > } >=20 > @@ -616,12 +618,15 @@ EnableReadOnlyPageWriteProtect ( > VOID > ) > { > + IA32_CR0 Cr0; > // > // To avoid unforseen consequences, don't touch paging settings in SMM > mode > // in this driver. > // > if (!IsInSmm ()) { > - AsmWriteCr0 (AsmReadCr0 () | CR0_WP); > + Cr0.UintN =3D AsmReadCr0 (); > + Cr0.Bits.WP =3D 1; > + AsmWriteCr0 (Cr0.UintN); > } > } >=20 > -- > 2.21.0.windows.1