From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: eric.dong@intel.com) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by groups.io with SMTP; Thu, 01 Aug 2019 18:20:38 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Aug 2019 18:20:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,336,1559545200"; d="scan'208";a="173086978" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga008.fm.intel.com with ESMTP; 01 Aug 2019 18:20:37 -0700 Received: from fmsmsx152.amr.corp.intel.com (10.18.125.5) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 1 Aug 2019 18:20:36 -0700 Received: from shsmsx107.ccr.corp.intel.com (10.239.4.96) by FMSMSX152.amr.corp.intel.com (10.18.125.5) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 1 Aug 2019 18:20:36 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.19]) by SHSMSX107.ccr.corp.intel.com ([169.254.9.65]) with mapi id 14.03.0439.000; Fri, 2 Aug 2019 09:20:34 +0800 From: "Dong, Eric" To: "Ni, Ray" , "devel@edk2.groups.io" CC: Laszlo Ersek Subject: Re: [PATCH v4 3/8] UefiCpuPkg/CpuDxe: Support parsing 5-level page table Thread-Topic: [PATCH v4 3/8] UefiCpuPkg/CpuDxe: Support parsing 5-level page table Thread-Index: AQHVSE/LWrEN0Xz6TEut6/c+Yc7X+abnEFJw Date: Fri, 2 Aug 2019 01:20:33 +0000 Message-ID: References: <20190801095831.274356-1-ray.ni@intel.com> <20190801095831.274356-4-ray.ni@intel.com> In-Reply-To: <20190801095831.274356-4-ray.ni@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: eric.dong@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong > -----Original Message----- > From: Ni, Ray > Sent: Thursday, August 1, 2019 5:58 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Laszlo Ersek > Subject: [PATCH v4 3/8] UefiCpuPkg/CpuDxe: Support parsing 5-level page > table >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2008 >=20 > Signed-off-by: Ray Ni > Cc: Eric Dong > Cc: Laszlo Ersek > --- > UefiCpuPkg/CpuDxe/CpuPageTable.c | 18 +++++++++++++++++- > UefiCpuPkg/CpuDxe/CpuPageTable.h | 3 ++- > 2 files changed, 19 insertions(+), 2 deletions(-) >=20 > diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c > b/UefiCpuPkg/CpuDxe/CpuPageTable.c > index 16a2528b55..36ce90d66c 100644 > --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c > +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c > @@ -184,6 +184,9 @@ GetCurrentPagingContext ( > if (Cr4.Bits.PAE !=3D 0) { > mPagingContext.ContextData.Ia32.Attributes |=3D > PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE; > } > + if (Cr4.Bits.LA57 !=3D 0) { > + mPagingContext.ContextData.Ia32.Attributes |=3D > PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_5_LEVEL; > + } >=20 > AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); > if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) { @@ -273,14 +276,17 @@ > GetPageTableEntry ( > UINTN Index2; > UINTN Index3; > UINTN Index4; > + UINTN Index5; > UINT64 *L1PageTable; > UINT64 *L2PageTable; > UINT64 *L3PageTable; > UINT64 *L4PageTable; > + UINT64 *L5PageTable; > UINT64 AddressEncMask; >=20 > ASSERT (PagingContext !=3D NULL); >=20 > + Index5 =3D ((UINTN)RShiftU64 (Address, 48)) & PAGING_PAE_INDEX_MASK; > Index4 =3D ((UINTN)RShiftU64 (Address, 39)) & PAGING_PAE_INDEX_MASK; > Index3 =3D ((UINTN)Address >> 30) & PAGING_PAE_INDEX_MASK; > Index2 =3D ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK; @@ - > 291,7 +297,17 @@ GetPageTableEntry ( > AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) > & PAGING_1G_ADDRESS_MASK_64; >=20 > if (PagingContext->MachineType =3D=3D IMAGE_FILE_MACHINE_X64) { > - L4PageTable =3D (UINT64 *)(UINTN)PagingContext- > >ContextData.X64.PageTableBase; > + if ((PagingContext->ContextData.X64.Attributes & > PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_5_LEVEL) !=3D 0) > { > + L5PageTable =3D (UINT64 *)(UINTN)PagingContext- > >ContextData.X64.PageTableBase; > + if (L5PageTable[Index5] =3D=3D 0) { > + *PageAttribute =3D PageNone; > + return NULL; > + } > + > + L4PageTable =3D (UINT64 *)(UINTN)(L5PageTable[Index5] & > ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64); > + } else { > + L4PageTable =3D (UINT64 *)(UINTN)PagingContext- > >ContextData.X64.PageTableBase; > + } > if (L4PageTable[Index4] =3D=3D 0) { > *PageAttribute =3D PageNone; > return NULL; > diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.h > b/UefiCpuPkg/CpuDxe/CpuPageTable.h > index 02d62f2b14..f845956f73 100644 > --- a/UefiCpuPkg/CpuDxe/CpuPageTable.h > +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.h > @@ -1,7 +1,7 @@ > /** @file > Page table management header file. >=20 > - Copyright (c) 2017, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -14,6 +14,7 @@ > #define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE > BIT0 > #define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE > BIT1 > #define > PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAGE_1G_SU > PPORT BIT2 > +#define > PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_5_LEVEL > BIT3 > #define > PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE > BIT30 > #define > PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATE > D BIT31 > // Other bits are reserved for future use > -- > 2.21.0.windows.1