From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: eric.dong@intel.com) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by groups.io with SMTP; Wed, 07 Aug 2019 23:27:11 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Aug 2019 23:27:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,360,1559545200"; d="scan'208";a="374744200" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga006.fm.intel.com with ESMTP; 07 Aug 2019 23:27:11 -0700 Received: from FMSMSX109.amr.corp.intel.com (10.18.116.9) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 7 Aug 2019 23:27:10 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx109.amr.corp.intel.com (10.18.116.9) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 7 Aug 2019 23:27:10 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.19]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.112]) with mapi id 14.03.0439.000; Thu, 8 Aug 2019 14:27:08 +0800 From: "Dong, Eric" To: "devel@edk2.groups.io" Subject: Re: [edk2-devel] [Patch v5 0/9] Support 5-level paging in DXE long mode Thread-Topic: [edk2-devel] [Patch v5 0/9] Support 5-level paging in DXE long mode Thread-Index: AQHVTbCc0uSEEpyg2UKmlFdCgbA8P6bwyNTA Date: Thu, 8 Aug 2019 06:27:08 +0000 Message-ID: References: <15B8DDEF808D3B5A.10910@groups.io> In-Reply-To: <15B8DDEF808D3B5A.10910@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: eric.dong@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Please ignore this serial which error adds "Signed-off-by: Eric Dong.." tag= by git tool. V6 serial has been send out. Thanks, Eric > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Dong, Eric > Sent: Thursday, August 8, 2019 2:15 PM > To: devel@edk2.groups.io > Subject: [edk2-devel] [Patch v5 0/9] Support 5-level paging in DXE long = mode >=20 > V5: > Correct the copyright time. > Update print format code. >=20 > v4: > Move all files under UefiCpuPkg/Include/Register/ to MdePkg. > NOTE: Changes like updating BaseLib.h to include Cpuid.h is not incl= uded. >=20 > v3: > Move UefiCpuPkg/Include/Register/Cpuid.h to > MdePkg/Include/Register/Intel/ directory. > Create UefiCpuPkg/Include/Register/Cpuid.h to include > MdePkg/Include/Register/Intel/Cpuid.h. > NOTE: > Changes like moving Amd/Cpuid.h to MdePkg is not included. > Changes like updating BaseLib.h to include Cpuid.h is not included= . >=20 > v2: > Refined the patch according to reviewers' all comments except: > 0A0h cannot be changed to A0h or build fails. > A big change in this patch is Cpuid.h is moved from UefiCpuPkg to Md= ePkg. > The move is based on real requirement when certain modules that cann= ot > depend on UefiCpuPkg but needs to reference structures defined in SD= M. >=20 >=20 > Eric Dong (1): > OvmfPkg/PlatformPei: Change referenced MSR name. >=20 > Ni, Ray (8): > UefiCpuPkg/MpInitLib: Enable 5-level paging for AP when BSP's enabled > UefiCpuPkg/CpuDxe: Remove unnecessary macros > UefiCpuPkg/CpuDxe: Support parsing 5-level page table > MdeModulePkg/DxeIpl: Introduce PCD PcdUse5LevelPageTable > MdePkg/Cpuid.h: Move Cpuid.h from UefiCpuPkg to MdePkg > MdeModulePkg/DxeIpl: Create 5-level page table for long mode > UefiCpuPkg|MdePkg: Move Register/ folder to MdePkg/Include/ > UefiCpuPkg: Update code to include register definitions from MdePkg >=20 > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 1 + > .../Core/DxeIplPeim/X64/VirtualMemory.c | 229 +- > MdeModulePkg/MdeModulePkg.dec | 7 + > MdeModulePkg/MdeModulePkg.uni | 7 + > .../Include/Register/Amd/Cpuid.h | 0 > .../Include/Register/Amd/Fam17Msr.h | 0 > .../Include/Register/Amd/Msr.h | 4 +- > .../Include/Register/Intel/ArchitecturalMsr.h | 6572 +++++++++++++++++ > MdePkg/Include/Register/Intel/Cpuid.h | 3997 ++++++++++ > MdePkg/Include/Register/Intel/LocalApic.h | 183 + > MdePkg/Include/Register/Intel/Microcode.h | 194 + > MdePkg/Include/Register/Intel/Msr.h | 44 + > .../Include/Register/Intel}/Msr/AtomMsr.h | 4 +- > .../Register/Intel}/Msr/BroadwellMsr.h | 4 +- > .../Include/Register/Intel}/Msr/Core2Msr.h | 4 +- > .../Include/Register/Intel}/Msr/CoreMsr.h | 4 +- > .../Include/Register/Intel}/Msr/GoldmontMsr.h | 4 +- > .../Register/Intel}/Msr/GoldmontPlusMsr.h | 4 +- > .../Include/Register/Intel}/Msr/HaswellEMsr.h | 4 +- > .../Include/Register/Intel}/Msr/HaswellMsr.h | 4 +- > .../Register/Intel}/Msr/IvyBridgeMsr.h | 4 +- > .../Include/Register/Intel}/Msr/NehalemMsr.h | 4 +- > .../Include/Register/Intel}/Msr/P6Msr.h | 4 +- > .../Include/Register/Intel}/Msr/Pentium4Msr.h | 4 +- > .../Include/Register/Intel}/Msr/PentiumMMsr.h | 4 +- > .../Include/Register/Intel}/Msr/PentiumMsr.h | 4 +- > .../Register/Intel}/Msr/SandyBridgeMsr.h | 4 +- > .../Register/Intel}/Msr/SilvermontMsr.h | 4 +- > .../Include/Register/Intel}/Msr/SkylakeMsr.h | 4 +- > .../Include/Register/Intel}/Msr/Xeon5600Msr.h | 4 +- > .../Include/Register/Intel}/Msr/XeonDMsr.h | 4 +- > .../Include/Register/Intel}/Msr/XeonE7Msr.h | 4 +- > .../Include/Register/Intel}/Msr/XeonPhiMsr.h | 4 +- > .../Register/Intel/SmramSaveStateMap.h | 184 + > MdePkg/Include/Register/Intel/StmApi.h | 948 +++ > .../Register/Intel}/StmResourceDescriptor.h | 6 +- > .../Include/Register/Intel}/StmStatusCode.h | 6 +- > OvmfPkg/PlatformPei/FeatureControl.c | 4 +- > UefiCpuPkg/Application/Cpuid/Cpuid.c | 2 +- > UefiCpuPkg/CpuDxe/CpuDxe.h | 4 +- > UefiCpuPkg/CpuDxe/CpuPageTable.c | 63 +- > UefiCpuPkg/CpuDxe/CpuPageTable.h | 3 +- > UefiCpuPkg/CpuMpPei/CpuPaging.c | 6 +- > .../Include/Library/RegisterCpuFeaturesLib.h | 2 +- > .../Include/Library/SmmCpuFeaturesLib.h | 2 +- > UefiCpuPkg/Include/Protocol/SmMonitorInit.h | 4 +- > .../Include/Register/ArchitecturalMsr.h | 6565 +--------------- > UefiCpuPkg/Include/Register/Cpuid.h | 3988 +--------- > UefiCpuPkg/Include/Register/LocalApic.h | 175 +- > UefiCpuPkg/Include/Register/Microcode.h | 187 +- > UefiCpuPkg/Include/Register/Msr.h | 36 +- > .../Include/Register/SmramSaveStateMap.h | 179 +- > UefiCpuPkg/Include/Register/StmApi.h | 941 +-- > .../Library/BaseXApicLib/BaseXApicLib.c | 6 +- > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 6 +- > .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 6 +- > UefiCpuPkg/Library/MpInitLib/MpLib.c | 13 + > UefiCpuPkg/Library/MpInitLib/MpLib.h | 12 +- > UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc | 3 +- > UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 14 +- > UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 4 +- > .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 6 +- > UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 6 +- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 4 +- > UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 2 - > 65 files changed, 12471 insertions(+), 12238 deletions(-) rename > {UefiCpuPkg =3D> MdePkg}/Include/Register/Amd/Cpuid.h (100%) rename > {UefiCpuPkg =3D> MdePkg}/Include/Register/Amd/Fam17Msr.h (100%) > rename {UefiCpuPkg =3D> MdePkg}/Include/Register/Amd/Msr.h (78%) > create mode 100644 MdePkg/Include/Register/Intel/ArchitecturalMsr.h > create mode 100644 MdePkg/Include/Register/Intel/Cpuid.h > create mode 100644 MdePkg/Include/Register/Intel/LocalApic.h > create mode 100644 MdePkg/Include/Register/Intel/Microcode.h > create mode 100644 MdePkg/Include/Register/Intel/Msr.h > rename {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/AtomMsr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/BroadwellMsr.h (95%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/Core2Msr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/CoreMsr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/GoldmontMsr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/GoldmontPlusMsr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/HaswellEMsr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/HaswellMsr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/IvyBridgeMsr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/NehalemMsr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/P6Msr.h (95%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/Pentium4Msr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/PentiumMMsr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/PentiumMsr.h (93%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/SandyBridgeMsr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/SilvermontMsr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/SkylakeMsr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/Xeon5600Msr.h (94%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/XeonDMsr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/XeonE7Msr.h (96%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/Msr/XeonPhiMsr.h (96%) create mode > 100644 MdePkg/Include/Register/Intel/SmramSaveStateMap.h > create mode 100644 MdePkg/Include/Register/Intel/StmApi.h > rename {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/StmResourceDescriptor.h (92%) rename > {UefiCpuPkg/Include/Register =3D> > MdePkg/Include/Register/Intel}/StmStatusCode.h (94%) >=20 > -- > 2.21.0.windows.1 >=20 >=20 >=20