From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.27256.1577675132732722257 for ; Sun, 29 Dec 2019 19:05:32 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: eric.dong@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Dec 2019 19:05:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,373,1571727600"; d="scan'208";a="420240715" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga006.fm.intel.com with ESMTP; 29 Dec 2019 19:05:31 -0800 Received: from fmsmsx124.amr.corp.intel.com (10.18.125.39) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 29 Dec 2019 19:05:31 -0800 Received: from shsmsx105.ccr.corp.intel.com (10.239.4.158) by fmsmsx124.amr.corp.intel.com (10.18.125.39) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 29 Dec 2019 19:05:31 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.202]) by SHSMSX105.ccr.corp.intel.com ([169.254.11.28]) with mapi id 14.03.0439.000; Mon, 30 Dec 2019 11:05:29 +0800 From: "Dong, Eric" To: "devel@edk2.groups.io" , "Wu, Hao A" CC: "Ni, Ray" , Laszlo Ersek , "Zeng, Star" , "Fu, Siyuan" , "Kinney, Michael D" Subject: Re: [edk2-devel] [PATCH v4 3/6] UefiCpuPkg: Add definitions for EDKII microcode patch HOB Thread-Topic: [edk2-devel] [PATCH v4 3/6] UefiCpuPkg: Add definitions for EDKII microcode patch HOB Thread-Index: AQHVvIfW/JadA9YLGEaRR3pDO2OC6KfSAtmg Date: Mon, 30 Dec 2019 03:05:28 +0000 Message-ID: References: <20191227073229.9416-1-hao.a.wu@intel.com> <20191227073229.9416-4-hao.a.wu@intel.com> In-Reply-To: <20191227073229.9416-4-hao.a.wu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: eric.dong@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Wu, Hao A > Sent: Friday, December 27, 2019 3:32 PM > To: devel@edk2.groups.io > Cc: Wu, Hao A ; Dong, Eric ; Ni= , > Ray ; Laszlo Ersek ; Zeng, Star > ; Fu, Siyuan ; Kinney, Michael > D > Subject: [edk2-devel] [PATCH v4 3/6] UefiCpuPkg: Add definitions for EDK= II > microcode patch HOB >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2430 >=20 > This commit will add the definitions for EDKII microcode patch HOB. >=20 > The intention of adding this HOB is to provide a scheme to store the bel= ow > information: >=20 > A. The base address and size of the microcode patches that are being > loaded (from flash) into memory; > B. The information of detected microcode patch for each processor within > the system. >=20 > The producer of the HOB will be the UefiCpuPkg/MpInitLib (where the load= , > detect and apply of the microcode happen). The consumer of the HOB can > be modules that want to detect/apply the microcode patch by themselves > again later during the boot flow. >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > Cc: Star Zeng > Cc: Siyuan Fu > Cc: Michael D Kinney > Signed-off-by: Hao A Wu > Reviewed-by: Ray Ni > --- > UefiCpuPkg/UefiCpuPkg.dec | 3 ++ > UefiCpuPkg/Include/Guid/MicrocodePatchHob.h | 44 > ++++++++++++++++++++ > 2 files changed, 47 insertions(+) >=20 > diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec > index 797f948631..45b267ac61 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dec > +++ b/UefiCpuPkg/UefiCpuPkg.dec > @@ -63,6 +63,9 @@ [Guids] > ## Include/Guid/CpuFeaturesInitDone.h > gEdkiiCpuFeaturesInitDoneGuid =3D { 0xc77c3a41, 0x61ab, 0x4143, { 0x= 98, > 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }} >=20 > + ## Include/Guid/MicrocodePatchHob.h > + gEdkiiMicrocodePatchHobGuid =3D { 0xd178f11d, 0x8716, 0x418e, { 0x= a1, > 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }} > + > [Protocols] > ## Include/Protocol/SmmCpuService.h > gEfiSmmCpuServiceProtocolGuid =3D { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x= 94, > 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }} diff --git > a/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h > b/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h > new file mode 100644 > index 0000000000..2d307fbffb > --- /dev/null > +++ b/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h > @@ -0,0 +1,44 @@ > +/** @file > + The microcode patch HOB is used to store the information of: > + A. Base address and size of the loaded microcode patches data; > + B. Detected microcode patch for each processor within system. > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _MICROCODE_PATCH_HOB_H_ > +#define _MICROCODE_PATCH_HOB_H_ > + > +extern EFI_GUID gEdkiiMicrocodePatchHobGuid; > + > +// > +// The EDKII microcode patch HOB will be produced by MpInitLib and it > +can be // consumed by modules that want to detect/apply microcode > patches. > +// > +typedef struct { > + // > + // The base address of the microcode patches data after being loaded > +into > + // memory. > + // > + UINT64 MicrocodePatchAddress; > + // > + // The total size of the loaded microcode patches. > + // > + UINT64 MicrocodePatchRegionSize; > + // > + // The number of processors within the system. > + // > + UINT32 ProcessorCount; > + // > + // An array with 'ProcessorCount' elements that stores the offset > +(with > + // regard to 'MicrocodePatchAddress') of the detected microcode patch > + // (including the CPU_MICROCODE_HEADER data structure) for each > processor. > + // If no microcode patch is detected for certain processor, the > +relating > + // element will be set to MAX_UINT64. > + // > + UINT64 ProcessorSpecificPatchOffset[0]; > +} EDKII_MICROCODE_PATCH_HOB; > + > +#endif > -- > 2.12.0.windows.1 >=20 >=20 >=20