From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web10.2727.1577755041583393624 for ; Mon, 30 Dec 2019 17:17:21 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: eric.dong@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Dec 2019 17:17:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,377,1571727600"; d="scan'208";a="213482349" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga008.jf.intel.com with ESMTP; 30 Dec 2019 17:17:20 -0800 Received: from fmsmsx161.amr.corp.intel.com (10.18.125.9) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 30 Dec 2019 17:17:20 -0800 Received: from shsmsx108.ccr.corp.intel.com (10.239.4.97) by FMSMSX161.amr.corp.intel.com (10.18.125.9) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 30 Dec 2019 17:17:20 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.202]) by SHSMSX108.ccr.corp.intel.com ([169.254.8.39]) with mapi id 14.03.0439.000; Tue, 31 Dec 2019 09:17:18 +0800 From: "Dong, Eric" To: "devel@edk2.groups.io" , "Wu, Hao A" CC: "Ni, Ray" , Laszlo Ersek , "Zeng, Star" , "Fu, Siyuan" , "Kinney, Michael D" Subject: Re: [edk2-devel] [PATCH v5 4/6] UefiCpuPkg/MpInitLib: Produce EDKII microcode patch HOB Thread-Topic: [edk2-devel] [PATCH v5 4/6] UefiCpuPkg/MpInitLib: Produce EDKII microcode patch HOB Thread-Index: AQHVv3Qo0i4cE9rGpEqsulMKbELE9KfTcRcg Date: Tue, 31 Dec 2019 01:17:18 +0000 Message-ID: References: <20191231004914.8520-1-hao.a.wu@intel.com> <20191231004914.8520-5-hao.a.wu@intel.com> In-Reply-To: <20191231004914.8520-5-hao.a.wu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: eric.dong@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Wu, Hao A > Sent: Tuesday, December 31, 2019 8:49 AM > To: devel@edk2.groups.io > Cc: Wu, Hao A ; Dong, Eric ; Ni= , > Ray ; Laszlo Ersek ; Zeng, Star > ; Fu, Siyuan ; Kinney, Michael > D > Subject: [edk2-devel] [PATCH v5 4/6] UefiCpuPkg/MpInitLib: Produce EDKII > microcode patch HOB >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2430 >=20 > This commit will update the MpInitLib to: >=20 > A. Collect the base address and size information after microcode patches > being loaded into memory; > B. Collect the detected microcode patch for each processor within system= ; C. > Based on the collected information, produce the EDKII microcode patch > HOB. >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > Cc: Star Zeng > Cc: Siyuan Fu > Cc: Michael D Kinney > Signed-off-by: Hao A Wu > --- > UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 1 + > UefiCpuPkg/Library/MpInitLib/MpLib.h | 24 +++++++-- > UefiCpuPkg/Library/MpInitLib/Microcode.c | 20 +++++-- > UefiCpuPkg/Library/MpInitLib/MpLib.c | 8 ++- > UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 55 ++++++++++++++++++++ > 5 files changed, 100 insertions(+), 8 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf > b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf > index 1538185ef9..326703cc9a 100644 > --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf > +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf > @@ -63,3 +63,4 @@ [Pcd] >=20 > [Guids] > gEdkiiS3SmmInitDoneGuid > + gEdkiiMicrocodePatchHobGuid > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h > b/UefiCpuPkg/Library/MpInitLib/MpLib.h > index 56b0df664a..885656900c 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h > @@ -138,6 +138,7 @@ typedef struct { > EFI_EVENT WaitEvent; > UINT32 ProcessorSignature; > UINT8 PlatformId; > + UINT64 MicrocodeEntryAddr; > } CPU_AP_DATA; >=20 > // > @@ -580,13 +581,15 @@ CheckAndUpdateApsStatus ( > /** > Detect whether specified processor can find matching microcode patch = and > load it. >=20 > - @param[in] CpuMpData The pointer to CPU MP Data structure. > - @param[in] IsBspCallIn Indicate whether the caller is BSP or not. > + @param[in] CpuMpData The pointer to CPU MP Data structure. > + @param[in] ProcessorNumber The handle number of the processor. The > range is > + from 0 to the total number of logical pr= ocessors > + minus 1. > **/ > VOID > MicrocodeDetect ( > IN CPU_MP_DATA *CpuMpData, > - IN BOOLEAN IsBspCallIn > + IN UINTN ProcessorNumber > ); >=20 > /** > @@ -619,5 +622,20 @@ EnableDebugAgent ( > VOID > ); >=20 > +/** > + Find the current Processor number by APIC ID. > + > + @param[in] CpuMpData Pointer to PEI CPU MP Data > + @param[out] ProcessorNumber Return the pocessor number found > + > + @retval EFI_SUCCESS ProcessorNumber is found and returned. > + @retval EFI_NOT_FOUND ProcessorNumber is not found. > +**/ > +EFI_STATUS > +GetProcessorNumber ( > + IN CPU_MP_DATA *CpuMpData, > + OUT UINTN *ProcessorNumber > + ); > + > #endif >=20 > diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c > b/UefiCpuPkg/Library/MpInitLib/Microcode.c > index 330fd99623..4162b4a8dc 100644 > --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c > +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c > @@ -65,13 +65,15 @@ GetCurrentMicrocodeSignature ( > It does not guarantee that the data has not been modified. > CPU has its own mechanism to verify Microcode Binary part. >=20 > - @param[in] CpuMpData The pointer to CPU MP Data structure. > - @param[in] IsBspCallIn Indicate whether the caller is BSP or not. > + @param[in] CpuMpData The pointer to CPU MP Data structure. > + @param[in] ProcessorNumber The handle number of the processor. The > range is > + from 0 to the total number of logical pr= ocessors > + minus 1. > **/ > VOID > MicrocodeDetect ( > IN CPU_MP_DATA *CpuMpData, > - IN BOOLEAN IsBspCallIn > + IN UINTN ProcessorNumber > ) > { > UINT32 ExtendedTableLength; > @@ -93,6 +95,7 @@ MicrocodeDetect ( > MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; > UINT32 ProcessorFlags; > UINT32 ThreadId; > + BOOLEAN IsBspCallIn; >=20 > // > // set ProcessorFlags to suppress incorrect compiler/analyzer warning= s @@ > -107,6 +110,7 @@ MicrocodeDetect ( > } >=20 > CurrentRevision =3D GetCurrentMicrocodeSignature (); > + IsBspCallIn =3D (ProcessorNumber =3D=3D (UINTN)CpuMpData->BspNumb= er) ? > TRUE : FALSE; > if (CurrentRevision !=3D 0 && !IsBspCallIn) { > // > // Skip loading microcode if it has been loaded successfully @@ -29= 5,6 > +299,16 @@ MicrocodeDetect ( > } while (((UINTN) MicrocodeEntryPoint < MicrocodeEnd)); >=20 > Done: > + if (LatestRevision !=3D 0) { > + // > + // Save the detected microcode patch entry address (including the > + // microcode patch header) for each processor. > + // It will be used when building the microcode patch cache HOB. > + // > + CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr =3D > + (UINTN) MicrocodeData - sizeof (CPU_MICROCODE_HEADER); } > + > if (LatestRevision > CurrentRevision) { > // > // BIOS only authenticate updates that contain a numerically larger= revision > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c > b/UefiCpuPkg/Library/MpInitLib/MpLib.c > index c72bf3c9ee..e611a8ca40 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c > @@ -399,12 +399,16 @@ ApInitializeSync ( > ) > { > CPU_MP_DATA *CpuMpData; > + UINTN ProcessorNumber; > + EFI_STATUS Status; >=20 > CpuMpData =3D (CPU_MP_DATA *) Buffer; > + Status =3D GetProcessorNumber (CpuMpData, &ProcessorNumber); > + ASSERT_EFI_ERROR (Status); > // > // Load microcode on AP > // > - MicrocodeDetect (CpuMpData, FALSE); > + MicrocodeDetect (CpuMpData, ProcessorNumber); > // > // Sync BSP's MTRR table to AP > // > @@ -1761,7 +1765,7 @@ MpInitLibInitialize ( > // > // Detect and apply Microcode on BSP > // > - MicrocodeDetect (CpuMpData, TRUE); > + MicrocodeDetect (CpuMpData, CpuMpData->BspNumber); > // > // Store BSP's MTRR setting > // > diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > index 3999603c3e..06e3f5d0d3 100644 > --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > @@ -9,6 +9,7 @@ > #include "MpLib.h" > #include > #include > +#include >=20 > /** > S3 SMM Init Done notification function. > @@ -291,6 +292,59 @@ CheckAndUpdateApsStatus ( } >=20 > /** > + Build the microcode patch HOB that contains the base address and size > + of the microcode patch stored in the memory. > + > + @param[in] CpuMpData Pointer to the CPU_MP_DATA structure. > + > +**/ > +VOID > +BuildMicrocodeCacheHob ( > + IN CPU_MP_DATA *CpuMpData > + ) > +{ > + EDKII_MICROCODE_PATCH_HOB *MicrocodeHob; > + UINTN HobDataLength; > + UINT32 Index; > + > + HobDataLength =3D sizeof (EDKII_MICROCODE_PATCH_HOB) + > + sizeof (UINT64) * CpuMpData->CpuCount; > + > + MicrocodeHob =3D AllocatePool (HobDataLength); if (MicrocodeHob =3D= = =3D > + NULL) { > + ASSERT (FALSE); > + return; > + } > + > + // > + // Store the information of the memory region that holds the microcod= e > patches. > + // > + MicrocodeHob->MicrocodePatchAddress =3D CpuMpData- > >MicrocodePatchAddress; > + MicrocodeHob->MicrocodePatchRegionSize =3D > + CpuMpData->MicrocodePatchRegionSize; > + > + // > + // Store the detected microcode patch for each processor as well. > + // > + MicrocodeHob->ProcessorCount =3D CpuMpData->CpuCount; for (Index =3D= 0; > + Index < CpuMpData->CpuCount; Index++) { > + if (CpuMpData->CpuData[Index].MicrocodeEntryAddr !=3D 0) { > + MicrocodeHob->ProcessorSpecificPatchOffset[Index] =3D > + CpuMpData->CpuData[Index].MicrocodeEntryAddr - CpuMpData- > >MicrocodePatchAddress; > + } else { > + MicrocodeHob->ProcessorSpecificPatchOffset[Index] =3D MAX_UINT64; > + } > + } > + > + BuildGuidDataHob ( > + &gEdkiiMicrocodePatchHobGuid, > + MicrocodeHob, > + HobDataLength > + ); > + > + return; > +} > + > +/** > Initialize global data for MP support. >=20 > @param[in] CpuMpData The pointer to CPU MP Data structure. > @@ -302,6 +356,7 @@ InitMpGlobalData ( > { > EFI_STATUS Status; >=20 > + BuildMicrocodeCacheHob (CpuMpData); > SaveCpuMpData (CpuMpData); >=20 > /// > -- > 2.12.0.windows.1 >=20 >=20 >=20