From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web12.725.1581487743841506352 for ; Tue, 11 Feb 2020 22:09:03 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: eric.dong@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Feb 2020 22:09:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,428,1574150400"; d="scan'208";a="237618850" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga006.jf.intel.com with ESMTP; 11 Feb 2020 22:09:02 -0800 Received: from fmsmsx604.amr.corp.intel.com (10.18.126.84) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 11 Feb 2020 22:09:02 -0800 Received: from fmsmsx604.amr.corp.intel.com (10.18.126.84) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 11 Feb 2020 22:09:01 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Tue, 11 Feb 2020 22:09:01 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.126]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.158]) with mapi id 14.03.0439.000; Wed, 12 Feb 2020 14:08:59 +0800 From: "Dong, Eric" To: Ray Ni , "devel@edk2.groups.io" CC: "Ni, Ray" , "Zeng, Star" , "Kinney, Michael D" Subject: Re: [PATCH v2 3/3] UefiCpuPkg/CpuFeature: Introduce First to indicate 1st unit. Thread-Topic: [PATCH v2 3/3] UefiCpuPkg/CpuFeature: Introduce First to indicate 1st unit. Thread-Index: AQHVpCEqDDftC2vvJ0+hEmB+f8DkMagXjWkA Date: Wed, 12 Feb 2020 06:08:58 +0000 Message-ID: References: <20191126061550.494828-1-niruiyu@users.noreply.github.com> <20191126061550.494828-4-niruiyu@users.noreply.github.com> In-Reply-To: <20191126061550.494828-4-niruiyu@users.noreply.github.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZTAxMTRhNjctNDE5NS00YjhiLTkwZGItMGNjZTY4MjFmOGE2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiakgzcExzeFwvYzZxTGd5NUIrZnBBanFZM01iR1RNYnRxMHRuZTNnRm1TZTB5Qyt0OFlZUkF6cUt3TUM1bTNWQUYifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: eric.dong@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong -----Original Message----- From: Ray Ni =20 Sent: Tuesday, November 26, 2019 2:16 PM To: devel@edk2.groups.io Cc: Ni, Ray ; Dong, Eric ; Zeng, Sta= r ; Kinney, Michael D Subject: [PATCH v2 3/3] UefiCpuPkg/CpuFeature: Introduce First to indicate = 1st unit. From: Ray Ni REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1584 The flow of CPU feature initialization logic is: 1. BSP calls GetConfigDataFunc() for each thread/AP; 2. Each thread/AP calls SupportFunc() to detect its own capability; 3. BSP calls InitializeFunc() for each thread/AP. There is a design gap in step #3. For a package scope feature that only requires one thread of each package does the initialization operation, what InitializeFunc() currently does is to do the initialization operation only CPU physical location Core# is 0. But in certain platform, Core#0 might be disabled in hardware level which results the certain package scope feature isn't initialized at all. The patch adds a new field Fist to indicate the CPU's location in its parent scope. First.Package is set for all APs/threads under first package; First.Core is set for all APs/threads under first core of each package; First.Thread is set for the AP/thread of each core. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Star Zeng Cc: Michael D Kinney --- .../Include/Library/RegisterCpuFeaturesLib.h | 36 +++++++++ .../CpuFeaturesInitialize.c | 74 +++++++++++++++++++ 2 files changed, 110 insertions(+) diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuP= kg/Include/Library/RegisterCpuFeaturesLib.h index d075606cdb..7114c8ce89 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -78,6 +78,37 @@ #define CPU_FEATURE_END MAX_UINT32 /// @} =20 +/// +/// The bit field to indicate whether the processor is the first in its pa= rent scope. +/// +typedef struct { + // + // Set to 1 when current processor is the first thread in the core it re= sides in. + // + UINT32 Thread : 1; + // + // Set to 1 when current processor is a thread of the first core in the = module it resides in. + // + UINT32 Core : 1; + // + // Set to 1 when current processor is a thread of the first module in th= e tile it resides in. + // + UINT32 Module : 1; + // + // Set to 1 when current processor is a thread of the first tile in the = die it resides in. + // + UINT32 Tile : 1; + // + // Set to 1 when current processor is a thread of the first die in the p= ackage it resides in. + // + UINT32 Die : 1; + // + // Set to 1 when current processor is a thread of the first package in t= he system. + // + UINT32 Package : 1; + UINT32 Reserved : 26; +} REGISTER_CPU_FEATURE_FIRST_PROCESSOR; + /// /// CPU Information passed into the SupportFunc and InitializeFunc of the /// RegisterCpuFeature() library function. This structure contains inform= ation @@ -88,6 +119,11 @@ typedef struct { /// The package that the CPU resides /// EFI_PROCESSOR_INFORMATION ProcessorInfo; + + /// + /// The bit flag indicating whether the CPU is the first Thread/Core/Mod= ule/Tile/Die/Package in its parent scope. + /// + REGISTER_CPU_FEATURE_FIRST_PROCESSOR First; /// /// The Display Family of the CPU computed from CPUID leaf CPUID_VERSION= _INFO /// diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitializ= e.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index 0a4fcff033..23076fd453 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -105,6 +105,9 @@ CpuInitDataInitialize ( EFI_CPU_PHYSICAL_LOCATION *Location; BOOLEAN *CoresVisited; UINTN Index; + UINT32 PackageIndex; + UINT32 CoreIndex; + UINT32 First; ACPI_CPU_DATA *AcpiCpuData; CPU_STATUS_INFORMATION *CpuStatus; UINT32 *ValidCoreCountPerPackage; @@ -234,6 +237,77 @@ CpuInitDataInitialize ( ASSERT (CpuFeaturesData->CpuFlags.CoreSemaphoreCount !=3D NULL); CpuFeaturesData->CpuFlags.PackageSemaphoreCount =3D AllocateZeroPool (si= zeof (UINT32) * CpuStatus->PackageCount * CpuStatus->MaxCoreCount * CpuStat= us->MaxThreadCount); ASSERT (CpuFeaturesData->CpuFlags.PackageSemaphoreCount !=3D NULL); + + // + // Initialize CpuFeaturesData->InitOrder[].CpuInfo.First + // + + // + // Set First.Package for each thread belonging to the first package. + // + First =3D MAX_UINT32; + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; ProcessorNum= ber++) { + Location =3D &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.Proc= essorInfo.Location; + First =3D MIN (Location->Package, First); + } + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; ProcessorNum= ber++) { + Location =3D &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.Proc= essorInfo.Location; + if (Location->Package =3D=3D First) { + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Package = =3D 1; + } + } + + // + // Set First.Die/Tile/Module for each thread assuming: + // single Die under each package, single Tile under each Die, single Mo= dule under each Tile + // + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; ProcessorNum= ber++) { + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Die =3D 1; + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Tile =3D 1; + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Module =3D 1= ; + } + + for (PackageIndex =3D 0; PackageIndex < CpuStatus->PackageCount; Package= Index++) { + // + // Set First.Core for each thread in the first core of each package. + // + First =3D MAX_UINT32; + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; ProcessorN= umber++) { + Location =3D &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.Pr= ocessorInfo.Location; + if (Location->Package =3D=3D PackageIndex) { + First =3D MIN (Location->Core, First); + } + } + + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; ProcessorN= umber++) { + Location =3D &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.Pr= ocessorInfo.Location; + if (Location->Package =3D=3D PackageIndex && Location->Core =3D=3D F= irst) { + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Core =3D= 1; + } + } + } + + for (PackageIndex =3D 0; PackageIndex < CpuStatus->PackageCount; Package= Index++) { + for (CoreIndex =3D 0; CoreIndex < CpuStatus->MaxCoreCount; CoreIndex++= ) { + // + // Set First.Thread for the first thread of each core. + // + First =3D MAX_UINT32; + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; Processo= rNumber++) { + Location =3D &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.= ProcessorInfo.Location; + if (Location->Package =3D=3D PackageIndex && Location->Core =3D=3D= CoreIndex) { + First =3D MIN (Location->Thread, First); + } + } + + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; Processo= rNumber++) { + Location =3D &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.= ProcessorInfo.Location; + if (Location->Package =3D=3D PackageIndex && Location->Core =3D=3D= CoreIndex && Location->Thread =3D=3D First) { + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Thread= =3D 1; + } + } + } + } } =20 /** --=20 2.21.0.windows.1