From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web08.8767.1649756169036405476 for ; Tue, 12 Apr 2022 02:36:10 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from lichao-PC (unknown [10.40.24.65]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dx3xAGSFViUzMgAA--.11144S2; Tue, 12 Apr 2022 17:36:06 +0800 (CST) Date: Tue, 12 Apr 2022 17:36:01 +0800 From: "Chao Li" To: "=?utf-8?Q?=22Chang=2C_Abner_(HPS_SW/FW_Technologist)=22?=" Cc: "=?utf-8?Q?=22devel=40edk2.groups.io=22?=" , Bob Feng , Liming Gao , Yuwei Chen , Baoqi Zhang Message-ID: In-Reply-To: References: Subject: Re: [edk2-devel] [staging/LoongArch RESEND PATCH v1 13/33] BaseTools: BaseTools changes for LoongArch platform. X-Mailer: Mailspring MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Dx3xAGSFViUzMgAA--.11144S2 X-Coremail-Antispam: 1UD129KBjvAXoWfCFW5Ww1kuw47tryktFy5Arb_yoW5Ar45Go W7Ka4xZw4kCaySkFZrG347WFsrKry8Gw1fJrZ8GF95GF1xKFs8CF4DJ3y8Zw1rJr40qan8 u3sFqayDAF98Kr15n29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUOm7k0a2IF6w4kM7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0 x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj4 1l84x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0 I7IYx2IY6xkF7I0E14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwV C2z280aVCY1x0267AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40Eb7x2 x7xS6r1j6r4UMc02F40EFcxC0VAKzVAqx4xG6I80ewAqx4xG64kEw2xG04xIwI0_Gr0_Xr 1l5I8CrVC2j2CEjI02ccxYII8I67AEr4CY67k08wAv7VC0I7IYx2IY67AKxVWUXVWUAwAv 7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMx 8GjcxK6IxK0xIIj40E5I8CrwCY02Avz4vE-syl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC 6x0Yz7v_Jr0_Gr1l4IxYO2xFxVAFwI0_Jw0_GFylx2IqxVAqx4xG67AKxVWUGVWUWwC20s 026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF 0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0x vE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv 6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxUys2-DUUUU X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQAOCF3QvPKQeQADsu Content-Type: multipart/alternative; boundary="62554801_660c9022_6697" --62554801_660c9022_6697 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Hi Anber, Please check my reply in the mail. -- Thanks, Chao ------------------------ On 4=E6=9C=88 8 2022, at 2:25 =E4=B8=8B=E5=8D=88, "Chang, Abner (HPS SW/FW = Technologist)" wrote: > > > > -----Original Message----- > > From: devel@edk2.groups.io On Behalf Of Chao Li > > Sent: Wednesday, February 9, 2022 2:55 PM > > To: devel@edk2.groups.io > > Cc: Bob Feng ; Liming Gao > > ; Yuwei Chen ; Baoqi > > Zhang > > Subject: [edk2-devel] [staging/LoongArch RESEND PATCH v1 13/33] > > BaseTools: BaseTools changes for LoongArch platform. > > > > C code changes for building EDK2 LoongArch platform. > > > > Cc: Bob Feng > > Cc: Liming Gao > > Cc: Yuwei Chen > > > > Signed-off-by: Chao Li > > Co-authored-by: Baoqi Zhang > > --- > > BaseTools/Source/C/Common/BasePeCoff.c | 15 +- > > BaseTools/Source/C/Common/PeCoffLoaderEx.c | 76 +++++++++ > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 ++++++++++++++- > > BaseTools/Source/C/GenFw/Elf64Convert.c | 153 +++++++++++++++++- > > BaseTools/Source/C/GenFw/elf_common.h | 58 +++++++ > > .../C/Include/IndustryStandard/PeImage.h | 57 ++++--- > > 6 files changed, 454 insertions(+), 33 deletions(-) > > > > diff --git a/BaseTools/Source/C/Common/BasePeCoff.c > > b/BaseTools/Source/C/Common/BasePeCoff.c > > index 62fbb2985c..30400d1341 100644 > > --- a/BaseTools/Source/C/Common/BasePeCoff.c > > +++ b/BaseTools/Source/C/Common/BasePeCoff.c > > @@ -5,6 +5,7 @@ > > Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
> > Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> > Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP.= All > > rights reserved.
> > +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. = All > > rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -68,6 +69,14 @@ PeCoffLoaderRelocateRiscVImage ( > > IN UINT64 Adjust > > ); > > > > +RETURN_STATUS > > +PeCoffLoaderRelocateLoongArch64Image ( > > + IN UINT16 *Reloc, > > + IN OUT CHAR8 *Fixup, > > + IN OUT CHAR8 **FixupData, > > + IN UINT64 Adjust > > + ); > > + > > STATIC > > RETURN_STATUS > > PeCoffLoaderGetPeHeader ( > > @@ -184,7 +193,8 @@ Returns: > > ImageContext->Machine !=3D EFI_IMAGE_MACHINE_ARMT && \ > > ImageContext->Machine !=3D EFI_IMAGE_MACHINE_EBC && \ > > ImageContext->Machine !=3D EFI_IMAGE_MACHINE_AARCH64 && \ > > - ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV64) { > > + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV64 && \ > > + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_LOONGARCH64) { > > if (ImageContext->Machine =3D=3D IMAGE_FILE_MACHINE_ARM) { > > // > > // There are two types of ARM images. Pure ARM and ARM/Thumb. > > @@ -815,6 +825,9 @@ Returns: > > case EFI_IMAGE_MACHINE_RISCV64: > > Status =3D PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupData, > > Adjust); > > break; > > + case EFI_IMAGE_MACHINE_LOONGARCH64: > > + Status =3D PeCoffLoaderRelocateLoongArch64Image (Reloc, Fixup, > > &FixupData, Adjust); > > + break; > > default: > > Status =3D RETURN_UNSUPPORTED; > > break; > > diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c > > b/BaseTools/Source/C/Common/PeCoffLoaderEx.c > > index 799f282970..b50ce8bdef 100644 > > --- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c > > +++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c > > @@ -4,6 +4,7 @@ IA32 and X64 Specific relocation fixups > > Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
> > Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> > Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts > > reserved.
> > +Copyright (c) 2022, Loongson Technology Corporation Limited. All right= s > > reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > --*/ > > @@ -332,3 +333,78 @@ PeCoffLoaderRelocateArmImage ( > > > > return RETURN_SUCCESS; > > } > > + > > +/** > > + Performs a LoongArch specific relocation fixup. > > + > > + @param Reloc Pointer to the relocation record. > > + @param Fixup Pointer to the address to fix up. > > + @param FixupData Pointer to a buffer to log the fixups. > > + @param Adjust The offset to adjust the fixup. > > + > > + @return Status code. > > +**/ > > +RETURN_STATUS > > +PeCoffLoaderRelocateLoongArch64Image ( > > + IN UINT16 *Reloc, > > + IN OUT CHAR8 *Fixup, > > + IN OUT CHAR8 **FixupData, > > + IN UINT64 Adjust > > + ) > > +{ > > + UINT8 RelocType; > > + UINT64 Value =3D 0; > > + UINT64 Tmp1 =3D 0; > > + UINT64 Tmp2 =3D 0; > > + > > + RelocType =3D ((*Reloc) >> 12); > > + > > + switch (RelocType) { > > + case EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA: > > + /* The next four instructions are used to load a 64 bit address, we > > change it together*/ > > + Value =3D (*(UINT32*)Fixup & 0x1ffffe0) << 7 | /* lu12i.w 20bits from > > bit5 */ > Please use double back slash for the comment in the function. So the comm= ent in the entire file look consistent. This applied to the changes in this= patch. > Chao: Okay, I will revise it in the next version. > + (*((UINT32*)Fixup + 1) & 0x3ffc00) >> 10; /* ori 12bits from bit10 */ > + Tmp1 =3D *((UINT32*)Fixup + 2) & 0x1ffffe0; /* lu32i.d 20bits from bit5 > */ > + Tmp2 =3D *((UINT32*)Fixup + 3) & 0x3ffc00; /* lu52i.d 12bits from > bit10 */ > + Value =3D Value | (Tmp1 << 27) | (Tmp2 << 42); > + > + Value +=3D Adjust; > + > + *(UINT32*)Fixup =3D (*(UINT32*)Fixup & ~0x1ffffe0) | (((Value >> 12) & > 0xfffff) << 5); > + if (*FixupData !=3D NULL) { > + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UINT32)); > + *(UINT32 *) (*FixupData) =3D *(UINT32*)Fixup; > + *FixupData =3D *FixupData + sizeof (UINT32); > + } > + > + Fixup +=3D sizeof(UINT32); > + *(UINT32*)Fixup =3D (*(UINT32*)Fixup & ~0x3ffc00) | ((Value & 0xfff) << > 10); > + if (*FixupData !=3D NULL) { > + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UINT32)); > + *(UINT32 *) (*FixupData) =3D *(UINT32*)Fixup; > + *FixupData =3D *FixupData + sizeof (UINT32); > + } > + > + Fixup +=3D sizeof(UINT32); > + *(UINT32*)Fixup =3D (*(UINT32*)Fixup & ~0x1ffffe0) | (((Value >> 32) & > 0xfffff) << 5); > + if (*FixupData !=3D NULL) { > + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UINT32)); > + *(UINT32 *) (*FixupData) =3D *(UINT32*)Fixup; > + *FixupData =3D *FixupData + sizeof (UINT32); > + } > + > + Fixup +=3D sizeof(UINT32); > + *(UINT32*)Fixup =3D (*(UINT32*)Fixup & ~0x3ffc00) | (((Value >> 52) & > 0xfff) << 10); > + if (*FixupData !=3D NULL) { > + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UINT32)); > + *(UINT32 *) (*FixupData) =3D *(UINT32*)Fixup; > + *FixupData =3D *FixupData + sizeof (UINT32); > + } > + break; > + default: > + Error (NULL, 0, 3000, "", "PeCoffLoaderRelocateLoongArch64Image: > Fixup[0x%x] Adjust[0x%llx] *Reloc[0x%x], type[0x%x].", *(UINT32*)Fixup, > Adjust, *Reloc, RelocType); > + return RETURN_UNSUPPORTED; > + } > + > + return RETURN_SUCCESS; > +} > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > index d650a527a5..9c518b3609 100644 > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > @@ -5,6 +5,7 @@ Copyright (c) 2004 - 2018, Intel Corporation. All rights > reserved.
> Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> Portions Copyright (c) 2016 HP Development Company, L.P.
> Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. A= ll > rights reserved.
> +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. Al= l > rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -57,6 +58,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > BOOLEAN mArm =3D FALSE; > BOOLEAN mRiscV =3D FALSE; > +BOOLEAN mLoongArch =3D FALSE; > STATIC UINT32 MaxFfsAlignment =3D 0; > BOOLEAN VtfFileFlag =3D FALSE; > > @@ -2416,6 +2418,102 @@ Returns: > return EFI_SUCCESS; > } > > +EFI_STATUS > +UpdateLoongArchResetVectorIfNeeded ( > + IN MEMORY_FILE *FvImage, > + IN FV_INFO *FvInfo > + ) > +/*++ > + > +Routine Description: > + This parses the FV looking for SEC and patches that address into the > + beginning of the FV header. > + > + For LoongArch ISA, the reset vector is at 0x1c000000. > + > + We relocate it to SecCoreEntry and copy the ResetVector code to the > + beginning of the FV. > + > +Arguments: > + FvImage Memory file for the FV memory image > + FvInfo Information read from INF file. > + > +Returns: > + > + EFI_SUCCESS Function Completed successfully. > + EFI_ABORTED Error encountered. > + EFI_INVALID_PARAMETER A required parameter was NULL. > + EFI_NOT_FOUND PEI Core file not found. > + > +--*/ > +{ > + EFI_STATUS Status; > + EFI_FILE_SECTION_POINTER SecPe32; > + BOOLEAN UpdateVectorSec =3D FALSE; > + UINT16 MachineType =3D 0; > + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress =3D 0; > + > + // > + // Verify input parameters > + // > + if (FvImage =3D=3D NULL || FvInfo =3D=3D NULL) { > + return EFI_INVALID_PARAMETER; > + } > + > + // > + // Locate an SEC Core instance and if found extract the machine type an= d > entry point address > + // > + Status =3D FindCorePeSection(FvImage->FileImage, FvInfo->Size, > EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32); > + if (!EFI_ERROR(Status)) { > + > + Status =3D GetCoreMachineType(SecPe32, &MachineType); > + if (EFI_ERROR(Status)) { > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type fo= r > SEC Core."); > + return EFI_ABORTED; > + } > + > + Status =3D GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, > SecPe32, &SecCoreEntryAddress); > + if (EFI_ERROR(Status)) { > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point > address for SEC Core."); > + return EFI_ABORTED; > + } > + > + UpdateVectorSec =3D TRUE; > + } > + > + if (!UpdateVectorSec) > + return EFI_SUCCESS; > + > + if (MachineType =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) { > + UINT32 ResetVector[3]; > + UINT32 InstrStack; > + > + memset(ResetVector, 0, sizeof (ResetVector)); > + > + /* if we found an SEC core entry point then generate a branch instructi= on > */ > + if (UpdateVectorSec) { > + VerboseMsg("UpdateLoongArchResetVectorIfNeeded updating > LOONGARCH64 SEC vector"); > + > + InstrStack =3D (SecCoreEntryAddress >> 12) & 0xfffff; > + ResetVector[0] =3D 0x14000001 | (InstrStack << 5); /* lu12i.w ra si20 *= / > + > + InstrStack =3D (SecCoreEntryAddress & 0x0fff); > + ResetVector[1] =3D 0x03800021 | (InstrStack << 10); /* ori ra, ra, ui12= */ > + ResetVector[2] =3D 0x4c000021; /* jirl ra, ra, 0 */ > + } > + > + // > + // Copy to the beginning of the FV > + // > + memcpy(FvImage->FileImage, ResetVector, sizeof (ResetVector)); > + } else { > + Error(NULL, 0, 3000, "Invalid", "Unknown machine type"); > + return EFI_ABORTED; > + } > + > + return EFI_SUCCESS; > +} > + > EFI_STATUS > GetPe32Info ( > IN UINT8 *Pe32, > @@ -2509,7 +2607,7 @@ Returns: > // > if ((*MachineType !=3D EFI_IMAGE_MACHINE_IA32) && (*MachineType !=3D > EFI_IMAGE_MACHINE_X64) && (*MachineType !=3D > EFI_IMAGE_MACHINE_EBC) && > (*MachineType !=3D EFI_IMAGE_MACHINE_ARMT) && (*MachineType !=3D > EFI_IMAGE_MACHINE_AARCH64) && > - (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV64)) { > + (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV64) && > (*MachineType !=3D EFI_IMAGE_MACHINE_LOONGARCH64)) { > Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE32 > file."); > return EFI_UNSUPPORTED; > } > @@ -2953,7 +3051,7 @@ Returns: > goto Finish; > } > > - if (!mArm && !mRiscV) { > + if (!mArm && !mRiscV && !mLoongArch) { > // > // Update reset vector (SALE_ENTRY for IPF) > // Now for IA32 and IA64 platform, the fv which has bsf file must have th= e > @@ -3004,6 +3102,19 @@ Returns: > FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, > FvHeader->HeaderLength / sizeof (UINT16)); > } > > + if (mLoongArch) { > + Status =3D UpdateLoongArchResetVectorIfNeeded (&FvImageMemoryFile, > &mFvDataInfo); > + if (EFI_ERROR (Status)) { > + Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector."); > + goto Finish; > + } > + // > + // Update Checksum for FvHeader > + // > + FvHeader->Checksum =3D 0; > + FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, > FvHeader->HeaderLength / sizeof (UINT16)); > + } > + > // > // Update FV Alignment attribute to the largest alignment of all the FFS = files > in the FV > // > @@ -3450,6 +3561,11 @@ Returns: > VerboseMsg("Located ARM/AArch64 SEC/PEI core in child FV"); > mArm =3D TRUE; > } > + // machine type is LOONGARCH64, set a flag so LOONGARCH64 reset > vector procesing occurs > + if ((MachineType =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64)) { > + VerboseMsg("Located LOONGARCH64 SEC core in child FV"); > + mLoongArch =3D TRUE; > + } > } > > // > @@ -3608,6 +3724,10 @@ Returns: > mRiscV =3D TRUE; > } > > + if ( (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) ) { > + mLoongArch =3D TRUE; > + } > + > // > // Keep Image Context for PE image in FV > // > @@ -3885,6 +4005,10 @@ Returns: > mArm =3D TRUE; > } > > + if ( (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) ) { > + mLoongArch =3D TRUE; > + } > + > // > // Keep Image Context for TE image in FV > // > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c > b/BaseTools/Source/C/GenFw/Elf64Convert.c > index 0bb3ead228..b66aadfd6c 100644 > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > @@ -4,6 +4,7 @@ Elf64 convert solution > Copyright (c) 2010 - 2021, Intel Corporation. All rights reserved.
> Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.
> Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. A= ll > rights reserved.
> +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. Al= l > rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -163,7 +164,7 @@ InitializeElf64 ( > Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or > ET_DYN"); > return FALSE; > } > - if (!((mEhdr->e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine =3D=3D > EM_AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64))) { > + if (!((mEhdr->e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine =3D=3D > EM_AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64) || (mEhdr- > >e_machine =3D=3D EM_LOONGARCH64))) { > Warning (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf64 > machine."); > } > if (mEhdr->e_version !=3D EV_CURRENT) { > @@ -730,6 +731,7 @@ ScanSections64 ( > case EM_X86_64: > case EM_AARCH64: > case EM_RISCV64: > + case EM_LOONGARCH64: > mCoffOffset +=3D sizeof (EFI_IMAGE_NT_HEADERS64); > break; > default: > @@ -943,6 +945,10 @@ ScanSections64 ( > NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_RISCV64; > NtHdr->Pe32Plus.OptionalHeader.Magic =3D > EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC; > break; > + case EM_LOONGARCH64: > + NtHdr->Pe32Plus.FileHeader.Machine =3D > EFI_IMAGE_MACHINE_LOONGARCH64; > + NtHdr->Pe32Plus.OptionalHeader.Magic =3D > EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC; > + break; > > default: > VerboseMsg ("%s unknown e_machine type. Assume X64", > (UINTN)mEhdr->e_machine); > @@ -1149,10 +1155,10 @@ WriteSections64 ( > } > > // > - // Skip error on EM_RISCV64 becasue no symble name is built > - // from RISC-V toolchain. > + // Skip error on EM_RISCV64 and EM_LOONGARCH64 becasue no > symble name is built > + // from RISC-V and LoongArch toolchain. > // > - if (mEhdr->e_machine !=3D EM_RISCV64) { > + if ((mEhdr->e_machine !=3D EM_RISCV64) && (mEhdr->e_machine !=3D > EM_LOONGARCH64)) { > Error (NULL, 0, 3000, "Invalid", > "%s: Bad definition for symbol '%s'@%#llx or unsupported symbol > type. " > "For example, absolute and undefined symbols are not > supported.", > @@ -1417,6 +1423,74 @@ WriteSections64 ( > // Write section for RISC-V 64 architecture. > // > WriteSectionRiscV64 (Rel, Targ, SymShdr, Sym); > + } else if (mEhdr->e_machine =3D=3D EM_LOONGARCH64) { > + switch (ELF_R_TYPE(Rel->r_info)) { > + > + case R_LARCH_SOP_PUSH_ABSOLUTE: > + // > + // Absolute relocation. > + // > + *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + > mCoffSectionsOffset[Sym->st_shndx]; > + break; > + > + case R_LARCH_MARK_LA: > + case R_LARCH_64: > + case R_LARCH_NONE: > + case R_LARCH_32: > + case R_LARCH_RELATIVE: > + case R_LARCH_COPY: > + case R_LARCH_JUMP_SLOT: > + case R_LARCH_TLS_DTPMOD32: > + case R_LARCH_TLS_DTPMOD64: > + case R_LARCH_TLS_DTPREL32: > + case R_LARCH_TLS_DTPREL64: > + case R_LARCH_TLS_TPREL32: > + case R_LARCH_TLS_TPREL64: > + case R_LARCH_IRELATIVE: > + case R_LARCH_MARK_PCREL: > + case R_LARCH_SOP_PUSH_PCREL: > + case R_LARCH_SOP_PUSH_DUP: > + case R_LARCH_SOP_PUSH_GPREL: > + case R_LARCH_SOP_PUSH_TLS_TPREL: > + case R_LARCH_SOP_PUSH_TLS_GOT: > + case R_LARCH_SOP_PUSH_TLS_GD: > + case R_LARCH_SOP_PUSH_PLT_PCREL: > + case R_LARCH_SOP_ASSERT: > + case R_LARCH_SOP_NOT: > + case R_LARCH_SOP_SUB: > + case R_LARCH_SOP_SL: > + case R_LARCH_SOP_SR: > + case R_LARCH_SOP_ADD: > + case R_LARCH_SOP_AND: > + case R_LARCH_SOP_IF_ELSE: > + case R_LARCH_SOP_POP_32_S_10_5: > + case R_LARCH_SOP_POP_32_U_10_12: > + case R_LARCH_SOP_POP_32_S_10_12: > + case R_LARCH_SOP_POP_32_S_10_16: > + case R_LARCH_SOP_POP_32_S_10_16_S2: > + case R_LARCH_SOP_POP_32_S_5_20: > + case R_LARCH_SOP_POP_32_S_0_5_10_16_S2: > + case R_LARCH_SOP_POP_32_S_0_10_10_16_S2: > + case R_LARCH_SOP_POP_32_U: > + case R_LARCH_ADD8: > + case R_LARCH_ADD16: > + case R_LARCH_ADD24: > + case R_LARCH_ADD32: > + case R_LARCH_ADD64: > + case R_LARCH_SUB8: > + case R_LARCH_SUB16: > + case R_LARCH_SUB24: > + case R_LARCH_SUB32: > + case R_LARCH_SUB64: > + case R_LARCH_GNU_VTINHERIT: > + case R_LARCH_GNU_VTENTRY: > + // > + // These types are not used or do not need to fix the offsets. > + // > + break; > + default: > + Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported > ELF EM_LOONGARCH64 relocation 0x%x.", mInImageName, (unsigned) > ELF64_R_TYPE(Rel->r_info)); > + } > } else { > Error (NULL, 0, 3000, "Invalid", "Not a supported machine type"); > } > @@ -1647,6 +1721,77 @@ WriteRelocations64 ( > default: > Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s > unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) > ELF_R_TYPE(Rel->r_info)); > } > + } else if (mEhdr->e_machine =3D=3D EM_LOONGARCH64) { > + switch (ELF_R_TYPE(Rel->r_info)) { > + case R_LARCH_MARK_LA: > + CoffAddFixup( > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] > + + (Rel->r_offset - SecShdr->sh_addr)), > + EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA); > + break; > + case R_LARCH_64: > + CoffAddFixup( > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] > + + (Rel->r_offset - SecShdr->sh_addr)), > + EFI_IMAGE_REL_BASED_DIR64); > + break; > + case R_LARCH_NONE: > + case R_LARCH_32: > + case R_LARCH_RELATIVE: > + case R_LARCH_COPY: > + case R_LARCH_JUMP_SLOT: > + case R_LARCH_TLS_DTPMOD32: > + case R_LARCH_TLS_DTPMOD64: > + case R_LARCH_TLS_DTPREL32: > + case R_LARCH_TLS_DTPREL64: > + case R_LARCH_TLS_TPREL32: > + case R_LARCH_TLS_TPREL64: > + case R_LARCH_IRELATIVE: > + case R_LARCH_MARK_PCREL: > + case R_LARCH_SOP_PUSH_PCREL: > + case R_LARCH_SOP_PUSH_ABSOLUTE: > + case R_LARCH_SOP_PUSH_DUP: > + case R_LARCH_SOP_PUSH_GPREL: > + case R_LARCH_SOP_PUSH_TLS_TPREL: > + case R_LARCH_SOP_PUSH_TLS_GOT: > + case R_LARCH_SOP_PUSH_TLS_GD: > + case R_LARCH_SOP_PUSH_PLT_PCREL: > + case R_LARCH_SOP_ASSERT: > + case R_LARCH_SOP_NOT: > + case R_LARCH_SOP_SUB: > + case R_LARCH_SOP_SL: > + case R_LARCH_SOP_SR: > + case R_LARCH_SOP_ADD: > + case R_LARCH_SOP_AND: > + case R_LARCH_SOP_IF_ELSE: > + case R_LARCH_SOP_POP_32_S_10_5: > + case R_LARCH_SOP_POP_32_U_10_12: > + case R_LARCH_SOP_POP_32_S_10_12: > + case R_LARCH_SOP_POP_32_S_10_16: > + case R_LARCH_SOP_POP_32_S_10_16_S2: > + case R_LARCH_SOP_POP_32_S_5_20: > + case R_LARCH_SOP_POP_32_S_0_5_10_16_S2: > + case R_LARCH_SOP_POP_32_S_0_10_10_16_S2: > + case R_LARCH_SOP_POP_32_U: > + case R_LARCH_ADD8: > + case R_LARCH_ADD16: > + case R_LARCH_ADD24: > + case R_LARCH_ADD32: > + case R_LARCH_ADD64: > + case R_LARCH_SUB8: > + case R_LARCH_SUB16: > + case R_LARCH_SUB24: > + case R_LARCH_SUB32: > + case R_LARCH_SUB64: > + case R_LARCH_GNU_VTINHERIT: > + case R_LARCH_GNU_VTENTRY: > + // > + // These types are not used or do not require fixup in PE format > files. > + // > + break; > + default: > + Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s > unsupported ELF EM_LOONGARCH64 relocation 0x%x.", mInImageName, > (unsigned) ELF64_R_TYPE(Rel->r_info)); > + } > } else { > Error (NULL, 0, 3000, "Not Supported", "This tool does not support > relocations for ELF with e_machine %u (processor type).", (unsigned) mEhd= r- > >e_machine); > } > diff --git a/BaseTools/Source/C/GenFw/elf_common.h > b/BaseTools/Source/C/GenFw/elf_common.h > index b67f59e7a0..34c8748f39 100644 > --- a/BaseTools/Source/C/GenFw/elf_common.h > +++ b/BaseTools/Source/C/GenFw/elf_common.h > @@ -4,6 +4,7 @@ Ported ELF include files from FreeBSD > Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.
> Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> Portion Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l > rights reserved.
> +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. Al= l > rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent > > > @@ -181,6 +182,7 @@ typedef struct { > #define EM_AARCH64 183 /* ARM 64bit Architecture */ > #define EM_RISCV64 243 /* 64bit RISC-V Architecture */ > #define EM_RISCV 244 /* 32bit RISC-V Architecture */ > +#define EM_LOONGARCH64 258 /* LoongArch 64-bit Architecture */ Do you have 32-bit LOONGARCH that also requires a value in spec? Abner Chao: I fact we only applied one value in Binutils that 258. I have been mo= dified this on our internal repo. Next version, I will have it sync ed to o= ur internal repo content, it should be: #define EM_LOONGARCH 258 /* LoongAr= ch Architecture */ > > /* Non-standard or deprecated. */ > #define EM_486 6 /* Intel i486. */ > @@ -1042,4 +1044,60 @@ typedef struct { > #define R_RISCV_SET8 54 > #define R_RISCV_SET16 55 > #define R_RISCV_SET32 56 > + > +/* > + * LoongArch relocation types > + */ > +#define R_LARCH_NONE 0 > +#define R_LARCH_32 1 > +#define R_LARCH_64 2 > +#define R_LARCH_RELATIVE 3 > +#define R_LARCH_COPY 4 > +#define R_LARCH_JUMP_SLOT 5 > +#define R_LARCH_TLS_DTPMOD32 6 > +#define R_LARCH_TLS_DTPMOD64 7 > +#define R_LARCH_TLS_DTPREL32 8 > +#define R_LARCH_TLS_DTPREL64 9 > +#define R_LARCH_TLS_TPREL32 10 > +#define R_LARCH_TLS_TPREL64 11 > +#define R_LARCH_IRELATIVE 12 > +#define R_LARCH_MARK_LA 20 > +#define R_LARCH_MARK_PCREL 21 > +#define R_LARCH_SOP_PUSH_PCREL 22 > +#define R_LARCH_SOP_PUSH_ABSOLUTE 23 > +#define R_LARCH_SOP_PUSH_DUP 24 > +#define R_LARCH_SOP_PUSH_GPREL 25 > +#define R_LARCH_SOP_PUSH_TLS_TPREL 26 > +#define R_LARCH_SOP_PUSH_TLS_GOT 27 > +#define R_LARCH_SOP_PUSH_TLS_GD 28 > +#define R_LARCH_SOP_PUSH_PLT_PCREL 29 > +#define R_LARCH_SOP_ASSERT 30 > +#define R_LARCH_SOP_NOT 31 > +#define R_LARCH_SOP_SUB 32 > +#define R_LARCH_SOP_SL 33 > +#define R_LARCH_SOP_SR 34 > +#define R_LARCH_SOP_ADD 35 > +#define R_LARCH_SOP_AND 36 > +#define R_LARCH_SOP_IF_ELSE 37 > +#define R_LARCH_SOP_POP_32_S_10_5 38 > +#define R_LARCH_SOP_POP_32_U_10_12 39 > +#define R_LARCH_SOP_POP_32_S_10_12 40 > +#define R_LARCH_SOP_POP_32_S_10_16 41 > +#define R_LARCH_SOP_POP_32_S_10_16_S2 42 > +#define R_LARCH_SOP_POP_32_S_5_20 43 > +#define R_LARCH_SOP_POP_32_S_0_5_10_16_S2 44 > +#define R_LARCH_SOP_POP_32_S_0_10_10_16_S2 45 > +#define R_LARCH_SOP_POP_32_U 46 > +#define R_LARCH_ADD8 47 > +#define R_LARCH_ADD16 48 > +#define R_LARCH_ADD24 49 > +#define R_LARCH_ADD32 50 > +#define R_LARCH_ADD64 51 > +#define R_LARCH_SUB8 52 > +#define R_LARCH_SUB16 53 > +#define R_LARCH_SUB24 54 > +#define R_LARCH_SUB32 55 > +#define R_LARCH_SUB64 56 > +#define R_LARCH_GNU_VTINHERIT 57 > +#define R_LARCH_GNU_VTENTRY 58 > #endif /* !_SYS_ELF_COMMON_H_ */ > diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h > b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h > index f17b8ee19b..80961e5576 100644 > --- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h > +++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h > @@ -7,6 +7,7 @@ > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights > reserved.
> + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights > reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -36,23 +37,25 @@ > // > // PE32+ Machine type for EFI images > // > -#define IMAGE_FILE_MACHINE_I386 0x014c > -#define IMAGE_FILE_MACHINE_EBC 0x0EBC > -#define IMAGE_FILE_MACHINE_X64 0x8664 > -#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only > -#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and > Thumb/Thumb 2 Little Endian > -#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM > Architecture, Little Endian > -#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA > +#define IMAGE_FILE_MACHINE_I386 0x014c > +#define IMAGE_FILE_MACHINE_EBC 0x0EBC > +#define IMAGE_FILE_MACHINE_X64 0x8664 > +#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only > +#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and > Thumb/Thumb 2 Little Endian > +#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM > Architecture, Little Endian > +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA > +#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264 // 64bit LoongArch > Architecture > > // > // Support old names for backward compatible > // > -#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386 > -#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC > -#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64 > -#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT > -#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64 > -#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64 > +#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386 > +#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC > +#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64 > +#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT > +#define EFI_IMAGE_MACHINE_AARCH64 > IMAGE_FILE_MACHINE_ARM64 > +#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64 > +#define EFI_IMAGE_MACHINE_LOONGARCH64 > IMAGE_FILE_MACHINE_LOONGARCH64 > > #define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ > #define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE > @@ -500,19 +503,21 @@ typedef struct { > // > // Based relocation types. > // > -#define EFI_IMAGE_REL_BASED_ABSOLUTE 0 > -#define EFI_IMAGE_REL_BASED_HIGH 1 > -#define EFI_IMAGE_REL_BASED_LOW 2 > -#define EFI_IMAGE_REL_BASED_HIGHLOW 3 > -#define EFI_IMAGE_REL_BASED_HIGHADJ 4 > -#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5 > -#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5 > -#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 > -#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7 > -#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 > -#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 > -#define EFI_IMAGE_REL_BASED_IA64_IMM64 9 > -#define EFI_IMAGE_REL_BASED_DIR64 10 > +#define EFI_IMAGE_REL_BASED_ABSOLUTE 0 > +#define EFI_IMAGE_REL_BASED_HIGH 1 > +#define EFI_IMAGE_REL_BASED_LOW 2 > +#define EFI_IMAGE_REL_BASED_HIGHLOW 3 > +#define EFI_IMAGE_REL_BASED_HIGHADJ 4 > +#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5 > +#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5 > +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 > +#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7 > +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 > +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 > +#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8 > +#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8 > +#define EFI_IMAGE_REL_BASED_IA64_IMM64 9 > +#define EFI_IMAGE_REL_BASED_DIR64 10 > > > /// > -- > 2.27.0 > > > >=20 > --62554801_660c9022_6697 Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline
Hi Anber,

Please check my reply in the mail.

--=
Thanks,
Chao
------------------------


On 4=E6=9C=88 8 2022, at 2= :25 =E4=B8=8B=E5=8D=88, "Chang, Abner (HPS SW/FW Technologist)" <abner.c= hang@hpe.com> wrote:


> -----Origin= al Message-----
> From: devel@edk2.groups.io <devel@edk2.gr= oups.io> On Behalf Of Chao Li
> Sent: Wednesday, February 9= , 2022 2:55 PM
> To: devel@edk2.groups.io
> Cc: B= ob Feng <bob.c.feng@intel.com>; Liming Gao
> <gaolimi= ng@byosoft.com.cn>; Yuwei Chen <yuwei.chen@intel.com>; Baoqi
=
> Zhang <zhangbaoqi@loongson.cn>
> Subject: [edk= 2-devel] [staging/LoongArch RESEND PATCH v1 13/33]
> BaseTools= : BaseTools changes for LoongArch platform.
>
> C= code changes for building EDK2 LoongArch platform.
>
> Cc: Bob Feng <bob.c.feng@intel.com>
> Cc: Liming = Gao <gaoliming@byosoft.com.cn>
> Cc: Yuwei Chen <yuwe= i.chen@intel.com>
>
> Signed-off-by: Chao Li &= lt;lichao@loongson.cn>
> Co-authored-by: Baoqi Zhang <zh= angbaoqi@loongson.cn>
> ---
> BaseTools/Source= /C/Common/BasePeCoff.c | 15 +-
> BaseTools/Source/C/Common/PeC= offLoaderEx.c | 76 +++++++++
> BaseTools/Source/C/GenFv/GenFvI= nternalLib.c | 128 ++++++++++++++-
> BaseTools/Source/C/GenFw/= Elf64Convert.c | 153 +++++++++++++++++-
> BaseTools/Source/C/G= enFw/elf_common.h | 58 +++++++
> .../C/Include/IndustryStandar= d/PeImage.h | 57 ++++---
> 6 files changed, 454 insertions(+),= 33 deletions(-)
>
> diff --git a/BaseTools/Sourc= e/C/Common/BasePeCoff.c
> b/BaseTools/Source/C/Common/BasePeCo= ff.c
> index 62fbb2985c..30400d1341 100644
> --- = a/BaseTools/Source/C/Common/BasePeCoff.c
> +++ b/BaseTools/Sou= rce/C/Common/BasePeCoff.c
> @@ -5,6 +5,7 @@
> Cop= yright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
> Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reser= ved.<BR>
> Portions Copyright (c) 2020, Hewlett Packard = Enterprise Development LP. All
> rights reserved.<BR>
> +Portions Copyright (c) 2022, Loongson Technology Corporation = Limited. All
> rights reserved.<BR>
> SPDX-= License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -68,6 +69,14 @@ PeCoffLoaderRelocateRiscVImage (
> IN UINT64 Adjust
> );
>
> +RET= URN_STATUS
> +PeCoffLoaderRelocateLoongArch64Image (
> + IN UINT16 *Reloc,
> + IN OUT CHAR8 *Fixup,
&= gt; + IN OUT CHAR8 **FixupData,
> + IN UINT64 Adjust
> + );
> +
> STATIC
> RETURN_STA= TUS
> PeCoffLoaderGetPeHeader (
> @@ -184,7 +193,= 8 @@ Returns:
> ImageContext->Machine !=3D EFI_IMAGE_MACHIN= E_ARMT && \
> ImageContext->Machine !=3D EFI_IMAGE_= MACHINE_EBC && \
> ImageContext->Machine !=3D EFI_I= MAGE_MACHINE_AARCH64 && \
> - ImageContext->Machine= !=3D EFI_IMAGE_MACHINE_RISCV64) {
> + ImageContext->Machin= e !=3D EFI_IMAGE_MACHINE_RISCV64 && \
> + ImageContext= ->Machine !=3D EFI_IMAGE_MACHINE_LOONGARCH64) {
> if (Image= Context->Machine =3D=3D IMAGE_FILE_MACHINE_ARM) {
> //
> // There are two types of ARM images. Pure ARM and ARM/Thumb.
> @@ -815,6 +825,9 @@ Returns:
> case EFI_IMAGE_MAC= HINE_RISCV64:
> Status =3D PeCoffLoaderRelocateRiscVImage (Rel= oc, Fixup, &FixupData,
> Adjust);
> break;
> + case EFI_IMAGE_MACHINE_LOONGARCH64:
> + Status = =3D PeCoffLoaderRelocateLoongArch64Image (Reloc, Fixup,
> &= ;FixupData, Adjust);
> + break;
> default:
<= div>> Status =3D RETURN_UNSUPPORTED;
> break;
>= ; diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c
> b/= BaseTools/Source/C/Common/PeCoffLoaderEx.c
> index 799f282970.= .b50ce8bdef 100644
> --- a/BaseTools/Source/C/Common/PeCoffLoa= derEx.c
> +++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
> @@ -4,6 +4,7 @@ IA32 and X64 Specific relocation fixups
> Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.&= lt;BR>
> Portions Copyright (c) 2011 - 2013, ARM Ltd. All r= ights reserved.<BR>
> Copyright (c) 2020, Hewlett Packar= d Enterprise Development LP. All rights
> reserved.<BR><= /div>
> +Copyright (c) 2022, Loongson Technology Corporation Limited= . All rights
> reserved.<BR>
> SPDX-License= -Identifier: BSD-2-Clause-Patent
>
> --*/
> @@ -332,3 +333,78 @@ PeCoffLoaderRelocateArmImage (
><= /div>
> return RETURN_SUCCESS;
> }
> +
> +/**
> + Performs a LoongArch specific relocation = fixup.
> +
> + @param Reloc Pointer to the reloca= tion record.
> + @param Fixup Pointer to the address to fix up= .
> + @param FixupData Pointer to a buffer to log the fixups.<= /div>
> + @param Adjust The offset to adjust the fixup.
&g= t; +
> + @return Status code.
> +**/
&g= t; +RETURN_STATUS
> +PeCoffLoaderRelocateLoongArch64Image (
> + IN UINT16 *Reloc,
> + IN OUT CHAR8 *Fixup,
> + IN OUT CHAR8 **FixupData,
> + IN UINT64 Adjust
> + )
> +{
> + UINT8 RelocType;
<= div>> + UINT64 Value =3D 0;
> + UINT64 Tmp1 =3D 0;
> + UINT64 Tmp2 =3D 0;
> +
> + RelocType =3D= ((*Reloc) >> 12);
> +
> + switch (RelocTyp= e) {
> + case EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA:
> + /* The next four instructions are used to load a 64 bit address, = we
> change it together*/
> + Value =3D (*(UINT32= *)Fixup & 0x1ffffe0) << 7 | /* lu12i.w 20bits from
>= bit5 */
Please use double back slash for the comment in the func= tion. So the comment in the entire file look consistent. This applied to th= e changes in this patch.
  &nbs= p; Chao: Okay, I will revise it in the next version.

> + (*((UINT32*)Fixup + 1) & 0x3ffc00) >> 10; /* ori 12bits f= rom bit10 */
> + Tmp1 =3D *((UINT32*)Fixup + 2) & 0x1ffffe= 0; /* lu32i.d 20bits from bit5
> */
> + Tmp2 =3D = *((UINT32*)Fixup + 3) & 0x3ffc00; /* lu52i.d 12bits from
>= bit10 */
> + Value =3D Value | (Tmp1 << 27) | (Tmp2 <= ;< 42);
> +
> + Value +=3D Adjust;
&= gt; +
> + *(UINT32*)Fixup =3D (*(UINT32*)Fixup & ~0x1ffffe= 0) | (((Value >> 12) &
> 0xfffff) << 5);
=
> + if (*FixupData !=3D NULL) {
> + *FixupData =3D ALI= GN_POINTER (*FixupData, sizeof (UINT32));
> + *(UINT32 *) (*Fi= xupData) =3D *(UINT32*)Fixup;
> + *FixupData =3D *FixupData + = sizeof (UINT32);
> + }
> +
> + Fixup= +=3D sizeof(UINT32);
> + *(UINT32*)Fixup =3D (*(UINT32*)Fixup= & ~0x3ffc00) | ((Value & 0xfff) <<
> 10);
=
> + if (*FixupData !=3D NULL) {
> + *FixupData =3D ALI= GN_POINTER (*FixupData, sizeof (UINT32));
> + *(UINT32 *) (*Fi= xupData) =3D *(UINT32*)Fixup;
> + *FixupData =3D *FixupData + = sizeof (UINT32);
> + }
> +
> + Fixup= +=3D sizeof(UINT32);
> + *(UINT32*)Fixup =3D (*(UINT32*)Fixup= & ~0x1ffffe0) | (((Value >> 32) &
> 0xfffff) &l= t;< 5);
> + if (*FixupData !=3D NULL) {
> + *F= ixupData =3D ALIGN_POINTER (*FixupData, sizeof (UINT32));
> + = *(UINT32 *) (*FixupData) =3D *(UINT32*)Fixup;
> + *FixupData = =3D *FixupData + sizeof (UINT32);
> + }
> +
=
> + Fixup +=3D sizeof(UINT32);
> + *(UINT32*)Fixup =3D= (*(UINT32*)Fixup & ~0x3ffc00) | (((Value >> 52) &
= > 0xfff) << 10);
> + if (*FixupData !=3D NULL) {
> + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UINT32));
> + *(UINT32 *) (*FixupData) =3D *(UINT32*)Fixup;
>= + *FixupData =3D *FixupData + sizeof (UINT32);
> + }
> + break;
> + default:
> + Error (NULL, 0, = 3000, "", "PeCoffLoaderRelocateLoongArch64Image:
> Fixup[0x%x]= Adjust[0x%llx] *Reloc[0x%x], type[0x%x].", *(UINT32*)Fixup,
>= Adjust, *Reloc, RelocType);
> + return RETURN_UNSUPPORTED;
> + }
> +
> + return RETURN_SUCCESS;
> +}
> diff --git a/BaseTools/Source/C/GenFv/GenFv= InternalLib.c
> b/BaseTools/Source/C/GenFv/GenFvInternalLib.c<= /div>
> index d650a527a5..9c518b3609 100644
> --- a/Bas= eTools/Source/C/GenFv/GenFvInternalLib.c
> +++ b/BaseTools/Sou= rce/C/GenFv/GenFvInternalLib.c
> @@ -5,6 +5,7 @@ Copyright (c)= 2004 - 2018, Intel Corporation. All rights
> reserved.<BR&= gt;
> Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights = reserved.<BR>
> Portions Copyright (c) 2016 HP Developme= nt Company, L.P.<BR>
> Portions Copyright (c) 2020, Hewl= ett Packard Enterprise Development LP. All
> rights reserved.&= lt;BR>
> +Portions Copyright (c) 2022, Loongson Technology = Corporation Limited. All
> rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -57,6 +58,7 @@ SPDX-License-Identifier: BSD-2-= Clause-Patent
>
> BOOLEAN mArm =3D FALSE;
> BOOLEAN mRiscV =3D FALSE;
> +BOOLEAN mLoongArch =3D FA= LSE;
> STATIC UINT32 MaxFfsAlignment =3D 0;
> BOO= LEAN VtfFileFlag =3D FALSE;
>
> @@ -2416,6 +2418,= 102 @@ Returns:
> return EFI_SUCCESS;
> }
>
> +EFI_STATUS
> +UpdateLoongArchResetVect= orIfNeeded (
> + IN MEMORY_FILE *FvImage,
> + IN = FV_INFO *FvInfo
> + )
> +/*++
> +
> +Routine Description:
> + This parses the FV look= ing for SEC and patches that address into the
> + beginning of= the FV header.
> +
> + For LoongArch ISA, the re= set vector is at 0x1c000000.
> +
> + We relocate = it to SecCoreEntry and copy the ResetVector code to the
> + be= ginning of the FV.
> +
> +Arguments:
&g= t; + FvImage Memory file for the FV memory image
> + FvInfo In= formation read from INF file.
> +
> +Returns:
> +
> + EFI_SUCCESS Function Completed successfully.=
> + EFI_ABORTED Error encountered.
> + EFI_INVAL= ID_PARAMETER A required parameter was NULL.
> + EFI_NOT_FOUND = PEI Core file not found.
> +
> +--*/
&g= t; +{
> + EFI_STATUS Status;
> + EFI_FILE_SECTION= _POINTER SecPe32;
> + BOOLEAN UpdateVectorSec =3D FALSE;
=
> + UINT16 MachineType =3D 0;
> + EFI_PHYSICAL_ADDRESS= SecCoreEntryAddress =3D 0;
> +
> + //
= > + // Verify input parameters
> + //
> + if (= FvImage =3D=3D NULL || FvInfo =3D=3D NULL) {
> + return EFI_IN= VALID_PARAMETER;
> + }
> +
> + //
> + // Locate an SEC Core instance and if found extract the mach= ine type and
> entry point address
> + //
> + Status =3D FindCorePeSection(FvImage->FileImage, FvInfo->Si= ze,
> EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
= > + if (!EFI_ERROR(Status)) {
> +
> + Status = =3D GetCoreMachineType(SecPe32, &MachineType);
> + if (EFI= _ERROR(Status)) {
> + Error(NULL, 0, 3000, "Invalid", "Could n= ot get the PE32 machine type for
> SEC Core.");
>= + return EFI_ABORTED;
> + }
> +
> += Status =3D GetCoreEntryPointAddress(FvImage->FileImage, FvInfo,
> SecPe32, &SecCoreEntryAddress);
> + if (EFI_ERROR(= Status)) {
> + Error(NULL, 0, 3000, "Invalid", "Could not get = the PE32 entry point
> address for SEC Core.");
>= + return EFI_ABORTED;
> + }
> +
> += UpdateVectorSec =3D TRUE;
> + }
> +
&g= t; + if (!UpdateVectorSec)
> + return EFI_SUCCESS;
&= gt; +
> + if (MachineType =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64= ) {
> + UINT32 ResetVector[3];
> + UINT32 InstrSt= ack;
> +
> + memset(ResetVector, 0, sizeof (Reset= Vector));
> +
> + /* if we found an SEC core entr= y point then generate a branch instruction
> */
>= + if (UpdateVectorSec) {
> + VerboseMsg("UpdateLoongArchReset= VectorIfNeeded updating
> LOONGARCH64 SEC vector");
= > +
> + InstrStack =3D (SecCoreEntryAddress >> 12) &a= mp; 0xfffff;
> + ResetVector[0] =3D 0x14000001 | (InstrStack &= lt;< 5); /* lu12i.w ra si20 */
> +
> + InstrSt= ack =3D (SecCoreEntryAddress & 0x0fff);
> + ResetVector[1]= =3D 0x03800021 | (InstrStack << 10); /* ori ra, ra, ui12 */
> + ResetVector[2] =3D 0x4c000021; /* jirl ra, ra, 0 */
>= + }
> +
> + //
> + // Copy to the b= eginning of the FV
> + //
> + memcpy(FvImage->= FileImage, ResetVector, sizeof (ResetVector));
> + } else {
> + Error(NULL, 0, 3000, "Invalid", "Unknown machine type");
> + return EFI_ABORTED;
> + }
> +
=
> + return EFI_SUCCESS;
> +}
> +
> EFI_STATUS
> GetPe32Info (
> IN UINT8 *Pe3= 2,
> @@ -2509,7 +2607,7 @@ Returns:
> //
> if ((*MachineType !=3D EFI_IMAGE_MACHINE_IA32) && (*MachineT= ype !=3D
> EFI_IMAGE_MACHINE_X64) && (*MachineType != =3D
> EFI_IMAGE_MACHINE_EBC) &&
> (*Machi= neType !=3D EFI_IMAGE_MACHINE_ARMT) && (*MachineType !=3D
> EFI_IMAGE_MACHINE_AARCH64) &&
> - (*MachineType = !=3D EFI_IMAGE_MACHINE_RISCV64)) {
> + (*MachineType !=3D EFI_= IMAGE_MACHINE_RISCV64) &&
> (*MachineType !=3D EFI_IMA= GE_MACHINE_LOONGARCH64)) {
> Error (NULL, 0, 3000, "Invalid", = "Unrecognized machine type in the PE32
> file.");
&g= t; return EFI_UNSUPPORTED;
> }
> @@ -2953,7 +3051= ,7 @@ Returns:
> goto Finish;
> }
><= /div>
> - if (!mArm && !mRiscV) {
> + if (!mArm= && !mRiscV && !mLoongArch) {
> //
&= gt; // Update reset vector (SALE_ENTRY for IPF)
> // Now for I= A32 and IA64 platform, the fv which has bsf file must have the
&g= t; @@ -3004,6 +3102,19 @@ Returns:
> FvHeader->Checksum =3D= CalculateChecksum16 ((UINT16 *) FvHeader,
> FvHeader->Head= erLength / sizeof (UINT16));
> }
>
>= + if (mLoongArch) {
> + Status =3D UpdateLoongArchResetVector= IfNeeded (&FvImageMemoryFile,
> &mFvDataInfo);
> + if (EFI_ERROR (Status)) {
> + Error (NULL, 0, 3000, = "Invalid", "Could not update the reset vector.");
> + goto Fin= ish;
> + }
> + //
> + // Update Chec= ksum for FvHeader
> + //
> + FvHeader->Checksu= m =3D 0;
> + FvHeader->Checksum =3D CalculateChecksum16 ((U= INT16 *) FvHeader,
> FvHeader->HeaderLength / sizeof (UINT1= 6));
> + }
> +
> //
> /= / Update FV Alignment attribute to the largest alignment of all the FFS fil= es
> in the FV
> //
> @@ -3450,6 +35= 61,11 @@ Returns:
> VerboseMsg("Located ARM/AArch64 SEC/PEI co= re in child FV");
> mArm =3D TRUE;
> }
= > + // machine type is LOONGARCH64, set a flag so LOONGARCH64 reset
> vector procesing occurs
> + if ((MachineType =3D=3D= EFI_IMAGE_MACHINE_LOONGARCH64)) {
> + VerboseMsg("Located LOO= NGARCH64 SEC core in child FV");
> + mLoongArch =3D TRUE;
> + }
> }
>
> //
= > @@ -3608,6 +3724,10 @@ Returns:
> mRiscV =3D TRUE;
<= div>> }
>
> + if ( (ImageContext.Machine =3D= =3D EFI_IMAGE_MACHINE_LOONGARCH64) ) {
> + mLoongArch =3D TRUE= ;
> + }
> +
> //
> // K= eep Image Context for PE image in FV
> //
> @@ -3= 885,6 +4005,10 @@ Returns:
> mArm =3D TRUE;
> }
>
> + if ( (ImageContext.Machine =3D=3D EFI_IMAGE_= MACHINE_LOONGARCH64) ) {
> + mLoongArch =3D TRUE;
&g= t; + }
> +
> //
> // Keep Image Cont= ext for TE image in FV
> //
> diff --git a/BaseTo= ols/Source/C/GenFw/Elf64Convert.c
> b/BaseTools/Source/C/GenFw= /Elf64Convert.c
> index 0bb3ead228..b66aadfd6c 100644
> --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> +++ b/B= aseTools/Source/C/GenFw/Elf64Convert.c
> @@ -4,6 +4,7 @@ Elf64= convert solution
> Copyright (c) 2010 - 2021, Intel Corporati= on. All rights reserved.<BR>
> Portions copyright (c) 20= 13-2014, ARM Ltd. All rights reserved.<BR>
> Portions Co= pyright (c) 2020, Hewlett Packard Enterprise Development LP. All
= > rights reserved.<BR>
> +Portions Copyright (c) 2022= , Loongson Technology Corporation Limited. All
> rights reserv= ed.<BR>
>
> SPDX-License-Identifier: BSD-2-= Clause-Patent
>
> @@ -163,7 +164,7 @@ InitializeE= lf64 (
> Error (NULL, 0, 3000, "Unsupported", "ELF e_type not = ET_EXEC or
> ET_DYN");
> return FALSE;
= > }
> - if (!((mEhdr->e_machine =3D=3D EM_X86_64) || (mE= hdr->e_machine =3D=3D
> EM_AARCH64) || (mEhdr->e_machine= =3D=3D EM_RISCV64))) {
> + if (!((mEhdr->e_machine =3D=3D = EM_X86_64) || (mEhdr->e_machine =3D=3D
> EM_AARCH64) || (mE= hdr->e_machine =3D=3D EM_RISCV64) || (mEhdr-
> >e_machin= e =3D=3D EM_LOONGARCH64))) {
> Warning (NULL, 0, 3000, "Unsupp= orted", "ELF e_machine is not Elf64
> machine.");
&g= t; }
> if (mEhdr->e_version !=3D EV_CURRENT) {
&g= t; @@ -730,6 +731,7 @@ ScanSections64 (
> case EM_X86_64:
> case EM_AARCH64:
> case EM_RISCV64:
> = + case EM_LOONGARCH64:
> mCoffOffset +=3D sizeof (EFI_IMAGE_NT= _HEADERS64);
> break;
> default:
> @= @ -943,6 +945,10 @@ ScanSections64 (
> NtHdr->Pe32Plus.File= Header.Machine =3D EFI_IMAGE_MACHINE_RISCV64;
> NtHdr->Pe32= Plus.OptionalHeader.Magic =3D
> EFI_IMAGE_NT_OPTIONAL_HDR64_MA= GIC;
> break;
> + case EM_LOONGARCH64:
= > + NtHdr->Pe32Plus.FileHeader.Machine =3D
> EFI_IMAGE_M= ACHINE_LOONGARCH64;
> + NtHdr->Pe32Plus.OptionalHeader.Magi= c =3D
> EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
> + br= eak;
>
> default:
> VerboseMsg ("%s = unknown e_machine type. Assume X64",
> (UINTN)mEhdr->e_mach= ine);
> @@ -1149,10 +1155,10 @@ WriteSections64 (
&g= t; }
>
> //
> - // Skip error on EM_= RISCV64 becasue no symble name is built
> - // from RISC-V too= lchain.
> + // Skip error on EM_RISCV64 and EM_LOONGARCH64 bec= asue no
> symble name is built
> + // from RISC-V= and LoongArch toolchain.
> //
> - if (mEhdr->= e_machine !=3D EM_RISCV64) {
> + if ((mEhdr->e_machine !=3D= EM_RISCV64) && (mEhdr->e_machine !=3D
> EM_LOONGAR= CH64)) {
> Error (NULL, 0, 3000, "Invalid",
> "%s= : Bad definition for symbol '%s'@%#llx or unsupported symbol
>= type. "
> "For example, absolute and undefined symbols are no= t
> supported.",
> @@ -1417,6 +1423,74 @@ WriteSe= ctions64 (
> // Write section for RISC-V 64 architecture.
> //
> WriteSectionRiscV64 (Rel, Targ, SymShdr, Sym);=
> + } else if (mEhdr->e_machine =3D=3D EM_LOONGARCH64) {
> + switch (ELF_R_TYPE(Rel->r_info)) {
> +
> + case R_LARCH_SOP_PUSH_ABSOLUTE:
> + //
= > + // Absolute relocation.
> + //
> + *(UINT6= 4 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr +
> mCoffSe= ctionsOffset[Sym->st_shndx];
> + break;
> +
> + case R_LARCH_MARK_LA:
> + case R_LARCH_64:
> + case R_LARCH_NONE:
> + case R_LARCH_32:
> + case R_LARCH_RELATIVE:
> + case R_LARCH_COPY:
> + case R_LARCH_JUMP_SLOT:
> + case R_LARCH_TLS_DTPMOD32= :
> + case R_LARCH_TLS_DTPMOD64:
> + case R_LARCH= _TLS_DTPREL32:
> + case R_LARCH_TLS_DTPREL64:
> += case R_LARCH_TLS_TPREL32:
> + case R_LARCH_TLS_TPREL64:
=
> + case R_LARCH_IRELATIVE:
> + case R_LARCH_MARK_PCRE= L:
> + case R_LARCH_SOP_PUSH_PCREL:
> + case R_LA= RCH_SOP_PUSH_DUP:
> + case R_LARCH_SOP_PUSH_GPREL:
&= gt; + case R_LARCH_SOP_PUSH_TLS_TPREL:
> + case R_LARCH_SOP_PU= SH_TLS_GOT:
> + case R_LARCH_SOP_PUSH_TLS_GD:
> += case R_LARCH_SOP_PUSH_PLT_PCREL:
> + case R_LARCH_SOP_ASSERT:=
> + case R_LARCH_SOP_NOT:
> + case R_LARCH_SOP_S= UB:
> + case R_LARCH_SOP_SL:
> + case R_LARCH_SOP= _SR:
> + case R_LARCH_SOP_ADD:
> + case R_LARCH_S= OP_AND:
> + case R_LARCH_SOP_IF_ELSE:
> + case R_= LARCH_SOP_POP_32_S_10_5:
> + case R_LARCH_SOP_POP_32_U_10_12:<= /div>
> + case R_LARCH_SOP_POP_32_S_10_12:
> + case R_L= ARCH_SOP_POP_32_S_10_16:
> + case R_LARCH_SOP_POP_32_S_10_16_S= 2:
> + case R_LARCH_SOP_POP_32_S_5_20:
> + case R= _LARCH_SOP_POP_32_S_0_5_10_16_S2:
> + case R_LARCH_SOP_POP_32_= S_0_10_10_16_S2:
> + case R_LARCH_SOP_POP_32_U:
>= + case R_LARCH_ADD8:
> + case R_LARCH_ADD16:
> += case R_LARCH_ADD24:
> + case R_LARCH_ADD32:
> + = case R_LARCH_ADD64:
> + case R_LARCH_SUB8:
> + ca= se R_LARCH_SUB16:
> + case R_LARCH_SUB24:
> + cas= e R_LARCH_SUB32:
> + case R_LARCH_SUB64:
> + case= R_LARCH_GNU_VTINHERIT:
> + case R_LARCH_GNU_VTENTRY:
> + //
> + // These types are not used or do not need to = fix the offsets.
> + //
> + break;
>= + default:
> + Error (NULL, 0, 3000, "Invalid", "WriteSection= s64(): %s unsupported
> ELF EM_LOONGARCH64 relocation 0x%x.", = mInImageName, (unsigned)
> ELF64_R_TYPE(Rel->r_info));
> + }
> } else {
> Error (NULL, 0, 3000,= "Invalid", "Not a supported machine type");
> }
>= ; @@ -1647,6 +1721,77 @@ WriteRelocations64 (
> default:
=
> Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s
<= div>> unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsig= ned)
> ELF_R_TYPE(Rel->r_info));
> }
> + } else if (mEhdr->e_machine =3D=3D EM_LOONGARCH64) {
&= gt; + switch (ELF_R_TYPE(Rel->r_info)) {
> + case R_LARCH_M= ARK_LA:
> + CoffAddFixup(
> + (UINT32) ((UINT64) = mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offs= et - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_LOONGARCH6= 4_MARK_LA);
> + break;
> + case R_LARCH_64:
=
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSections= Offset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr-= >sh_addr)),
> + EFI_IMAGE_REL_BASED_DIR64);
> = + break;
> + case R_LARCH_NONE:
> + case R_LARCH_= 32:
> + case R_LARCH_RELATIVE:
> + case R_LARCH_C= OPY:
> + case R_LARCH_JUMP_SLOT:
> + case R_LARCH= _TLS_DTPMOD32:
> + case R_LARCH_TLS_DTPMOD64:
> += case R_LARCH_TLS_DTPREL32:
> + case R_LARCH_TLS_DTPREL64:
> + case R_LARCH_TLS_TPREL32:
> + case R_LARCH_TLS_T= PREL64:
> + case R_LARCH_IRELATIVE:
> + case R_LA= RCH_MARK_PCREL:
> + case R_LARCH_SOP_PUSH_PCREL:
>= ; + case R_LARCH_SOP_PUSH_ABSOLUTE:
> + case R_LARCH_SOP_PUSH_= DUP:
> + case R_LARCH_SOP_PUSH_GPREL:
> + case R_= LARCH_SOP_PUSH_TLS_TPREL:
> + case R_LARCH_SOP_PUSH_TLS_GOT:
> + case R_LARCH_SOP_PUSH_TLS_GD:
> + case R_LARCH= _SOP_PUSH_PLT_PCREL:
> + case R_LARCH_SOP_ASSERT:
&g= t; + case R_LARCH_SOP_NOT:
> + case R_LARCH_SOP_SUB:
> + case R_LARCH_SOP_SL:
> + case R_LARCH_SOP_SR:
> + case R_LARCH_SOP_ADD:
> + case R_LARCH_SOP_AND:
=
> + case R_LARCH_SOP_IF_ELSE:
> + case R_LARCH_SOP_POP= _32_S_10_5:
> + case R_LARCH_SOP_POP_32_U_10_12:
>= ; + case R_LARCH_SOP_POP_32_S_10_12:
> + case R_LARCH_SOP_POP_= 32_S_10_16:
> + case R_LARCH_SOP_POP_32_S_10_16_S2:
= > + case R_LARCH_SOP_POP_32_S_5_20:
> + case R_LARCH_SOP_PO= P_32_S_0_5_10_16_S2:
> + case R_LARCH_SOP_POP_32_S_0_10_10_16_= S2:
> + case R_LARCH_SOP_POP_32_U:
> + case R_LAR= CH_ADD8:
> + case R_LARCH_ADD16:
> + case R_LARCH= _ADD24:
> + case R_LARCH_ADD32:
> + case R_LARCH_= ADD64:
> + case R_LARCH_SUB8:
> + case R_LARCH_SU= B16:
> + case R_LARCH_SUB24:
> + case R_LARCH_SUB= 32:
> + case R_LARCH_SUB64:
> + case R_LARCH_GNU_= VTINHERIT:
> + case R_LARCH_GNU_VTENTRY:
> + //
> + // These types are not used or do not require fixup in PE f= ormat
> files.
> + //
> + break;
> + default:
> + Error (NULL, 0, 3000, "Invalid", "W= riteRelocations64(): %s
> unsupported ELF EM_LOONGARCH64 reloc= ation 0x%x.", mInImageName,
> (unsigned) ELF64_R_TYPE(Rel->= r_info));
> + }
> } else {
> Error (= NULL, 0, 3000, "Not Supported", "This tool does not support
> = relocations for ELF with e_machine %u (processor type).", (unsigned) mEhdr-=
> >e_machine);
> }
> diff --git = a/BaseTools/Source/C/GenFw/elf_common.h
> b/BaseTools/Source/C= /GenFw/elf_common.h
> index b67f59e7a0..34c8748f39 100644
> --- a/BaseTools/Source/C/GenFw/elf_common.h
> +++ b= /BaseTools/Source/C/GenFw/elf_common.h
> @@ -4,6 +4,7 @@ Porte= d ELF include files from FreeBSD
> Copyright (c) 2009 - 2010, = Apple Inc. All rights reserved.<BR>
> Portions Copyright= (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> Po= rtion Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All
> rights reserved.<BR>
> +Portions Copyright = (c) 2022, Loongson Technology Corporation Limited. All
> right= s reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-= Patent
>
>
> @@ -181,6 +182,7 @@ typ= edef struct {
> #define EM_AARCH64 183 /* ARM 64bit Architectu= re */
> #define EM_RISCV64 243 /* 64bit RISC-V Architecture */=
> #define EM_RISCV 244 /* 32bit RISC-V Architecture */
<= div>> +#define EM_LOONGARCH64 258 /* LoongArch 64-bit Architecture */
Do you have 32-bit LOONGARCH that also requires a value in spec?
Abner
Chao: I fact we only applied one value in B= inutils that 258. I have been modified this on our internal repo. Next vers= ion, I will have it sync ed to our internal repo content, it should be: #de= fine EM_LOONGARCH 258 /* LoongArch Architecture */
>
> /* Non-standard or deprecated. */
> #define EM_486 = 6 /* Intel i486. */
> @@ -1042,4 +1044,60 @@ typedef struct {<= /div>
> #define R_RISCV_SET8 54
> #define R_RISCV_SET16= 55
> #define R_RISCV_SET32 56
> +
>= +/*
> + * LoongArch relocation types
> + */
> +#define R_LARCH_NONE 0
> +#define R_LARCH_32 1
> +#define R_LARCH_64 2
> +#define R_LARCH_RELATIVE = 3
> +#define R_LARCH_COPY 4
> +#define R_LARCH_JU= MP_SLOT 5
> +#define R_LARCH_TLS_DTPMOD32 6
> +#d= efine R_LARCH_TLS_DTPMOD64 7
> +#define R_LARCH_TLS_DTPREL32 8=
> +#define R_LARCH_TLS_DTPREL64 9
> +#define R_L= ARCH_TLS_TPREL32 10
> +#define R_LARCH_TLS_TPREL64 11
> +#define R_LARCH_IRELATIVE 12
> +#define R_LARCH_MARK_L= A 20
> +#define R_LARCH_MARK_PCREL 21
> +#define = R_LARCH_SOP_PUSH_PCREL 22
> +#define R_LARCH_SOP_PUSH_ABSOLUTE= 23
> +#define R_LARCH_SOP_PUSH_DUP 24
> +#define= R_LARCH_SOP_PUSH_GPREL 25
> +#define R_LARCH_SOP_PUSH_TLS_TPR= EL 26
> +#define R_LARCH_SOP_PUSH_TLS_GOT 27
> +#= define R_LARCH_SOP_PUSH_TLS_GD 28
> +#define R_LARCH_SOP_PUSH_= PLT_PCREL 29
> +#define R_LARCH_SOP_ASSERT 30
> += #define R_LARCH_SOP_NOT 31
> +#define R_LARCH_SOP_SUB 32
=
> +#define R_LARCH_SOP_SL 33
> +#define R_LARCH_SOP_SR= 34
> +#define R_LARCH_SOP_ADD 35
> +#define R_LA= RCH_SOP_AND 36
> +#define R_LARCH_SOP_IF_ELSE 37
>= ; +#define R_LARCH_SOP_POP_32_S_10_5 38
> +#define R_LARCH_SOP= _POP_32_U_10_12 39
> +#define R_LARCH_SOP_POP_32_S_10_12 40
> +#define R_LARCH_SOP_POP_32_S_10_16 41
> +#define= R_LARCH_SOP_POP_32_S_10_16_S2 42
> +#define R_LARCH_SOP_POP_3= 2_S_5_20 43
> +#define R_LARCH_SOP_POP_32_S_0_5_10_16_S2 44
> +#define R_LARCH_SOP_POP_32_S_0_10_10_16_S2 45
> = +#define R_LARCH_SOP_POP_32_U 46
> +#define R_LARCH_ADD8 47
> +#define R_LARCH_ADD16 48
> +#define R_LARCH_ADD2= 4 49
> +#define R_LARCH_ADD32 50
> +#define R_LAR= CH_ADD64 51
> +#define R_LARCH_SUB8 52
> +#define= R_LARCH_SUB16 53
> +#define R_LARCH_SUB24 54
> += #define R_LARCH_SUB32 55
> +#define R_LARCH_SUB64 56
> +#define R_LARCH_GNU_VTINHERIT 57
> +#define R_LARCH_GNU= _VTENTRY 58
> #endif /* !_SYS_ELF_COMMON_H_ */
> = diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
> b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
&g= t; index f17b8ee19b..80961e5576 100644
> --- a/BaseTools/Sourc= e/C/Include/IndustryStandard/PeImage.h
> +++ b/BaseTools/Sourc= e/C/Include/IndustryStandard/PeImage.h
> @@ -7,6 +7,7 @@
=
> Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved= .<BR>
> Portions copyright (c) 2011 - 2013, ARM Ltd. All= rights reserved.<BR>
> Copyright (c) 2020, Hewlett Pack= ard Enterprise Development LP. All rights
> reserved.<BR>= ;
> + Copyright (c) 2022, Loongson Technology Corporation Limi= ted. All rights
> reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -36,23 +37,25 @@
> //
> // PE32+ Machine= type for EFI images
> //
> -#define IMAGE_FILE_M= ACHINE_I386 0x014c
> -#define IMAGE_FILE_MACHINE_EBC 0x0EBC
> -#define IMAGE_FILE_MACHINE_X64 0x8664
> -#define= IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
> -#define IMAGE_= FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and
> Thumb/Thumb = 2 Little Endian
> -#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // = 64bit ARM
> Architecture, Little Endian
> -#defin= e IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA
> +#de= fine IMAGE_FILE_MACHINE_I386 0x014c
> +#define IMAGE_FILE_MACH= INE_EBC 0x0EBC
> +#define IMAGE_FILE_MACHINE_X64 0x8664
<= div>> +#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
>= ; +#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and
= > Thumb/Thumb 2 Little Endian
> +#define IMAGE_FILE_MACHINE= _ARM64 0xAA64 // 64bit ARM
> Architecture, Little Endian
=
> +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA
> +#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264 // 64bit LoongA= rch
> Architecture
>
> //
= > // Support old names for backward compatible
> //
> -#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386
&= gt; -#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC
> -#= define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
> -#define= EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT
> -#define EFI= _IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64
> -#define EFI= _IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64
> +#define E= FI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386
> +#define EFI_I= MAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC
> +#define EFI_IMAGE_M= ACHINE_X64 IMAGE_FILE_MACHINE_X64
> +#define EFI_IMAGE_MACHINE= _ARMT IMAGE_FILE_MACHINE_ARMT
> +#define EFI_IMAGE_MACHINE_AAR= CH64
> IMAGE_FILE_MACHINE_ARM64
> +#define EFI_IM= AGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64
> +#define EFI_= IMAGE_MACHINE_LOONGARCH64
> IMAGE_FILE_MACHINE_LOONGARCH64
>
> #define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ
> #define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE
> @@ = -500,19 +503,21 @@ typedef struct {
> //
> // Bas= ed relocation types.
> //
> -#define EFI_IMAGE_RE= L_BASED_ABSOLUTE 0
> -#define EFI_IMAGE_REL_BASED_HIGH 1
=
> -#define EFI_IMAGE_REL_BASED_LOW 2
> -#define EFI_IM= AGE_REL_BASED_HIGHLOW 3
> -#define EFI_IMAGE_REL_BASED_HIGHADJ= 4
> -#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
>= ; -#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
> -#define EFI_IMA= GE_REL_BASED_RISCV_HI20 5
> -#define EFI_IMAGE_REL_BASED_ARM_M= OV32T 7
> -#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
> -#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
> -#define = EFI_IMAGE_REL_BASED_IA64_IMM64 9
> -#define EFI_IMAGE_REL_BASE= D_DIR64 10
> +#define EFI_IMAGE_REL_BASED_ABSOLUTE 0
> +#define EFI_IMAGE_REL_BASED_HIGH 1
> +#define EFI_IMAGE= _REL_BASED_LOW 2
> +#define EFI_IMAGE_REL_BASED_HIGHLOW 3
> +#define EFI_IMAGE_REL_BASED_HIGHADJ 4
> +#define E= FI_IMAGE_REL_BASED_MIPS_JMPADDR 5
> +#define EFI_IMAGE_REL_BAS= ED_ARM_MOV32A 5
> +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
> +#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7
> +#def= ine EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
> +#define EFI_IMAGE_RE= L_BASED_RISCV_LOW12S 8
> +#define EFI_IMAGE_REL_BASED_LOONGARC= H32_MARK_LA 8
> +#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_= LA 8
> +#define EFI_IMAGE_REL_BASED_IA64_IMM64 9
>= ; +#define EFI_IMAGE_REL_BASED_DIR64 10
>
>
=
> ///
> --
> 2.27.0
>
<= div>>
>
>
>
3D"Sent --62554801_660c9022_6697--