From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Neutral (access neither permitted nor denied) identity=mailfrom; client-ip=203.199.198.232; helo=imsva.in.megatrends.com; envelope-from=rameshr@ami.com; receiver=edk2-devel@lists.01.org Received: from IMSVA.IN.MEGATRENDS.COM (Webmail.amiindia.co.in [203.199.198.232]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CA72F210F30B4 for ; Wed, 15 Aug 2018 23:59:52 -0700 (PDT) Received: from IMSVA.IN.MEGATRENDS.COM (IMSVA.IN.MEGATRENDS.COM [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8C2ED8204A; Thu, 16 Aug 2018 12:34:22 +0530 (IST) Received: from IMSVA.IN.MEGATRENDS.COM (IMSVA.IN.MEGATRENDS.COM [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6BA0082047; Thu, 16 Aug 2018 12:34:21 +0530 (IST) Received: from webmail.amiindia.co.in (venus1.in.megatrends.com [10.0.0.5]) by IMSVA.IN.MEGATRENDS.COM (Postfix) with ESMTPS; Thu, 16 Aug 2018 12:34:21 +0530 (IST) Received: from VENUS2.in.megatrends.com ([fe80::2002:4a07:4f17:c09b]) by VENUS1.in.megatrends.com ([fe80::951:7975:6ecf:eae5%14]) with mapi id 14.01.0438.000; Thu, 16 Aug 2018 12:29:48 +0530 From: Ramesh R. To: "MohammadYounasKhan.P@Dell.com" , "ruiyu.ni@intel.com" , "edk2-devel@lists.01.org" Thread-Topic: Question regarding CMOS regions. Thread-Index: AdQwbXw0bU09G6E1SGqYwJK+xDH0yQCldFkAAABUloAAHxeNsABmsI1QAALlTaAAAFY8wAABTp4g Date: Thu, 16 Aug 2018 06:59:47 +0000 Message-ID: References: <1b14d8bcb83c4db48a7f4b72f8b8dff6@BLRX13MDC420.AMER.DELL.COM> <2d9aeae9d4c94b2c9c1f63161b94c9f5@BLRX13MDC420.AMER.DELL.COM> <734D49CCEBEEF84792F5B80ED585239D5BDD7A02@SHSMSX104.ccr.corp.intel.com> <907e738d5a3543c8a47738843877b3c1@BLRX13MDC420.AMER.DELL.COM> In-Reply-To: <907e738d5a3543c8a47738843877b3c1@BLRX13MDC420.AMER.DELL.COM> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.0.84.57] MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-TM-AS-Product-Ver: IMSVA-9.1.0.1817-8.2.0.1013-24034.005 X-TM-AS-Result: No--31.059-5.0-31-10 X-imss-scan-details: No--31.059-5.0-31-10 X-TMASE-Version: IMSVA-9.1.0.1817-8.2.1013-24034.005 X-TMASE-Result: 10--31.058600-10.000000 X-TMASE-MatchedRID: IDdx3MBO6ECROBVNmXUDuN35+5/2RxqmmX+W7bzPOQHoXwNg7KFUStfU JveoE4izSBo11xAnqZG3RKE0MAGqAMwdQieqpnTaiS2Zc5eDYqQ2O5Eh+45TR83J+h/wWLV9cBa 45GbRMhpFXcm/C/kiiWdoeFOwuPAx2oFQ+DjioMONzYJBKgDdEVctRqnPrLuBBX9nCl4coo8TPx VE0bfvLTYzmt/S9ABVbUXhxrsZF9yiM5lnplQeLNRZ1mKTfKthQKuv8uQBDjoVJCt21nV3ea1R2 Ccxxsa5zeL2GB7tFk1veXFB1aHeFiaHj+XQ22lLMIiU395I8H1zWwGH37l9g8naL1ri/ilXU9a6 zfLFA1Y5qDlhAYEFL0L6gSBtt0EASg2ZSwUn/Kv9KXlxhBAZb5hwKdlCfPk8StFk/81wIJKLOsW lYdMG9wR1ZtMYefFWPC7j/mzpDFpA7Hi290JnwlgowyUWHgGdh+w9Wz/xXDoR8rMICe0qkPMxs+ ucp3ZMyS4a/w19Mu+jsy4IyYQvCHAUwvUpRIyquWB2ZAowRT2/zKpacmFSwUENV4Lwnu7BmbcKR mzJEYVk5c9keGiG7Ftn3RgiTQk0ogpWPAdh/Tu4jAucHcCqnX17zx+CiSWzDC/Vm90If4VUzan9 xEPKMSCmmsI07TT42MSMtCciUY04c5PfPWZTtg6w00GeWBFafS0Ip2eEHnyvXSmSdlcYms8943o c3p3sJYy14nqCNssv7bm8B5Akl/oA9r2LThYYeSC65CityAyd+c1I3V2+zymP2doteTOWL4tIP4 zqlBab6vac+Nqd637cGd19dSFd X-TMASE-SNAP-Result: 1.821001.0001-0-1-12:0,22:0,33:0,34:0-0 X-Content-Filtered-By: Mailman/MimeDel 2.1.27 Subject: Re: Question regarding CMOS regions. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Aug 2018 06:59:53 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable 1) To check the Extended RAM validity. * Read the Offset 0 from Extended RTC Ram. * If no 0 value, extended RTC Ram is present. * If it's 0xFF, write some value to Offset 0 * Read it back. If you get the value that you wrote, extended RTC R= AM is present and preserve the old value again. * If you still get 0xFF, Extended RTC RAM is not present. 2) Extended RTC RAM is NOT duplicate of standard RTC RAM. It's up to BIOS v= endor how they use it. May be BIOS uses the extended RTC RAM as duplicate c= opy of the standard RTC RAM. Check the "Real Time Clock Registers" Section in the SB Spec. Thanks, Ramesh -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Moha= mmadYounasKhan.P@Dell.com Sent: 16 August 2018 11:59 To: ruiyu.ni@intel.com; edk2-devel@lists.01.org Subject: Re: [edk2] Question regarding CMOS regions. Thanks Ruiyu. I have some inconsistencies with CMOS regions. Even EDKII uses some CMOS re= gions. I have attached the CMOS dump took using RW tool below: Type:ISA Port 0070,0071 Width:01 00=3D56 01=3D17 02=3D45 03=3D17 04=3D11 05=3D15 06=3D04 07=3D16 08=3D08 09=3D18 0A=3D26 0B=3D02 0C=3D50 0D=3D80 0E=3D00 0F=3D00 10=3D00 11=3D00 12=3D00 13=3D00 14=3D00 15=3D7B 16=3D02 17=3DFF 18=3DFF 19= =3D00 1A=3D00 1B=3D00 1C=3D00 1D=3D00 1E=3D00 1F=3D00 20=3D00 21=3D00 22=3D00 23=3D00 24=3D00 25=3D00 26=3D00 27=3D00 28=3D00 29=3D00 2A=3D00 2B=3D00 2C=3D00 2D=3D00 2E=3D02 2F=3D7B 30=3DFF 31= =3DFF 32=3D20 33=3D00 34=3D00 35=3D9D 36=3D0B 37=3D00 38=3D00 39=3D00 3A=3D00 3B=3D00 3C=3D00 3D=3D00 3E=3D00 3F=3D00 40=3D00 41=3D00 42=3DCA 43=3DB8 44=3D6C 45=3D58 46=3D00 47=3D00 48=3D00 49=3D00 4A=3D00 4B=3D00 4C=3D00 4D=3D00 4E=3D00 4F=3D00 50=3D00 51=3D00 52=3D00 53=3D00 54=3D03 55=3D00 56=3D00 57=3D00 58=3D00 59=3D00 5A=3D00 5B=3D00 5C=3D00 5D=3D00 5E=3D00 5F=3D00 60=3D00 61=3D00 62=3D00 63=3D00 64=3D00 65=3D00 66=3D00 67=3D00 68=3D00 69=3D00 6A=3D00 6B=3D00 6C=3D01 6D=3D00 6E=3D00 6F=3DA5 70=3D00 71=3D00 72=3D00 73=3D00 74=3D00 75=3D00 76=3D00 77=3D00 78=3D00 79=3D5F 7A=3D00 7B=3D00 7C=3D00 7D=3D00 7E=3D00 7F=3D00 80=3D56 81=3D17 82=3D45 83=3D17 84=3D11 85=3D15 86=3D04 87=3D16 88=3D08 89=3D18 8A=3D26 8B=3D02 8C=3D40 8D=3D80 8E=3D00 8F=3D00 90=3D00 91=3D00 92=3D00 93=3D00 94=3D00 95=3D7B 96=3D02 97=3DFF 98=3DFF 99= =3D00 9A=3D00 9B=3D00 9C=3D00 9D=3D00 9E=3D00 9F=3D00 A0=3D00 A1=3D00 A2=3D00 A3=3D00 A4=3D00 A5=3D00 A6=3D00 A7=3D00 A8=3D00 A9=3D00 AA=3D00 AB=3D00 AC=3D00 AD=3D00 AE=3D02 AF=3D7B B0=3DFF B1= =3DFF B2=3D20 B3=3D00 B4=3D00 B5=3D9D B6=3D0B B7=3D00 B8=3D00 B9=3D00 BA=3D00 BB=3D00 BC=3D00 BD=3D00 BE=3D00 BF=3D00 C0=3D00 C1=3D00 C2=3DCA C3=3DB8 C4=3D6C C5=3D58 C6=3D00 C7=3D00 C8=3D00 C9=3D00 CA=3D00 CB=3D00 CC=3D00 CD=3D00 CE=3D00 CF=3D00 D0=3D00 D1=3D00 D2=3D00 D3=3D00 D4=3D03 D5=3D00 D6=3D00 D7=3D00 D8=3D00 D9=3D00 DA=3D00 DB=3D00 DC=3D00 DD=3D00 DE=3D00 DF=3D00 E0=3D00 E1=3D00 E2=3D00 E3=3D00 E4=3D00 E5=3D00 E6=3D00 E7=3D00 E8=3D00 E9=3D00 EA=3D00 EB=3D00 EC=3D01 ED=3D00 EE=3D00 EF=3DA5 F0=3D00 F1=3D00 F2=3D00 F3=3D00 F4=3D00 F5=3D00 F6=3D00 F7=3D00 F8=3D00 F9=3D5F FA=3D00 FB=3D00 FC=3D00 FD=3D00 FE=3D00 FF=3D00 I have update my queries below. Thank you, Younas. -----Original Message----- From: Ni, Ruiyu [mailto:ruiyu.ni@intel.com] Sent: Thursday, August 16, 2018 11:38 AM To: Pathan, MohammadYounasKhan; edk2-devel@lists.01.org Subject: RE: Question regarding CMOS regions. Younas, Why are you still working on CMOS in now UEFI world? Detailed answer is in below. Thanks/Ray > -----Original Message----- > From: edk2-devel > On Behalf Of > MohammadYounasKhan.P@Dell.com > Sent: Thursday, August 16, 2018 12:44 PM > To: edk2-devel@lists.01.org > Subject: Re: [edk2] Question regarding CMOS regions. > > Hi Guys, > > Please help to reply to my below queries. > > Thank you, > Younas. > > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Pathan, MohammadYounasKhan > Sent: Tuesday, August 14, 2018 9:17 AM > To: edk2-devel@lists.01.org > Subject: [edk2] FW: Question regarding CMOS regions. > > Hi All, > > As we know CMOS data can be 128 or 256 bytes. CMOS lower 128 bytes are > stored in IO ports 0x70-0x71 whereas CMOS upper 128 bytes are stored > using IO ports 0x72-0x73. > > 1. How to know that the system has 128bytes of CMOS or 256 bytes of > CMOS region? You could read the data to know whether high 128 bytes are valid or not. [Younas]: How to check the validity of data? > 2. Is there any CMOS location which represents CMOS upper region is > exists or valid or any other mechanism for it? Refer to #1. [Younas]: CMOS upper region means port 0x72-0x73. Each IO port can store 25= 6 bytes of data (0x00-0xFF). Default lower CMOS region has date and time an= d is valid always. But for upper CMOS region, I am not sure how to check wh= ether it is valid or not? > 3. Are we replicating lower 128 bytes to upper 128 bytes in CMOS > location > 0x70-0x71 (or 0x72-0x73)? If yes, Why are we doing that? It depends on BIOS implementation. I don't see any bios is duplicating the = contents. [Younas]: You can refer to my CMOS dump copied above which shows upper 128b= ytes have same information as lower 128bytes (of port 0x70-0x71). I would l= ike to know why we are doing this? > > Thank you, > Younas. > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel