From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: donald.kuo@intel.com) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by groups.io with SMTP; Mon, 12 Aug 2019 20:26:21 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Aug 2019 20:26:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,380,1559545200"; d="scan'208";a="194104415" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga001.fm.intel.com with ESMTP; 12 Aug 2019 20:26:21 -0700 Received: from fmsmsx604.amr.corp.intel.com (10.18.126.84) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 12 Aug 2019 20:26:21 -0700 Received: from fmsmsx604.amr.corp.intel.com (10.18.126.84) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 12 Aug 2019 20:26:20 -0700 Received: from shsmsx105.ccr.corp.intel.com (10.239.4.158) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Mon, 12 Aug 2019 20:26:19 -0700 Received: from shsmsx108.ccr.corp.intel.com ([169.254.8.163]) by SHSMSX105.ccr.corp.intel.com ([169.254.11.15]) with mapi id 14.03.0439.000; Tue, 13 Aug 2019 11:26:17 +0800 From: "Donald Kuo" To: "Dong, Eric" , "devel@edk2.groups.io" CC: "Ni, Ray" , "Zeng, Star" , "Chan, Amy" , "Chaganty, Rangasai V" Subject: Re: [PATCH] UefiCpuPkg: Adding a new TSC library by using CPUID(0x15) TSC leaf Thread-Topic: [PATCH] UefiCpuPkg: Adding a new TSC library by using CPUID(0x15) TSC leaf Thread-Index: AQHVUQBbm+TUprkOmU2SLRKbZZdBaab4WRXQgAAPT3A= Date: Tue, 13 Aug 2019 03:26:16 +0000 Message-ID: References: <20190812112315.11268-1-donald.kuo@intel.com> In-Reply-To: Accept-Language: zh-TW, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYTJlNWQ1YWYtNGVkMC00YjBmLTgzNDMtODdlYmJhMWNhMzk1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiVzQyXC94ZVpkY2g2SE9WNUxLcCs1N0ZaU05wcjVvcUtoUlUra29RbUVyUGFKOXlXOWZyMFdrR2w4SUhhNXZOcU0ifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: donald.kuo@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Eric, The CPUID Leaf 0x1:EDX.TSC[bit 4] is to check capability for IA32_TIME_STAM= P_COUNTER MSR and RDTSC instruction which defined in IA32 SDM chapter 17.17 And what we implement is based on IA32 SDM Chapter 18.7 for CPU core XTAL c= lock frequency which is from CPUID Leaf 0x15 and new TSC frequency =3D (ECX= , Core XTAL Frequency) * EBX/EAX So no need to check CPUID(0x01). Thanks, Donald > -----Original Message----- > From: Dong, Eric > Sent: Tuesday, August 13, 2019 10:27 AM > To: Kuo, Donald ; devel@edk2.groups.io > Cc: Ni, Ray ; Zeng, Star ; Chan, > Amy ; Chaganty, Rangasai V > > Subject: RE: [PATCH] UefiCpuPkg: Adding a new TSC library by using > CPUID(0x15) TSC leaf >=20 > Hi Donald, >=20 > Do you think it's necessary to check the TIME_STAMP_COUNTER capability > before using it? I see SDM has CPUID(0x01) which return the capability of > TIME_STAMP_COUNTER. >=20 > Thanks, > Eric >=20 > > -----Original Message----- > > From: Kuo, Donald > > Sent: Monday, August 12, 2019 7:23 PM > > To: devel@edk2.groups.io > > Cc: Ni, Ray ; Zeng, Star ; > > Dong, Eric ; Chan, Amy ; > > Chaganty, Rangasai V > > Subject: [PATCH] UefiCpuPkg: Adding a new TSC library by using > > CPUID(0x15) TSC leaf > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1909 > > > > Cc: Ray Ni > > Cc: Star Zeng > > Cc: Eric Dong > > Cc: Amy Chan > > Cc: Rangasai V Chaganty > > Signed-off-by: Donald Kuo > > --- > > .../Library/BaseCpuTimerLib/BaseCpuTimerLib.c | 40 +++ > > .../Library/BaseCpuTimerLib/BaseCpuTimerLib.inf | 35 +++ > > .../Library/BaseCpuTimerLib/BaseCpuTimerLib.uni | 16 ++ > > UefiCpuPkg/Library/BaseCpuTimerLib/CpuTimerLib.c | 272 > > +++++++++++++++++++++ > > UefiCpuPkg/UefiCpuPkg.dec | 8 + > > UefiCpuPkg/UefiCpuPkg.dsc | 1 + > > 6 files changed, 372 insertions(+) > > create mode 100644 > > UefiCpuPkg/Library/BaseCpuTimerLib/BaseCpuTimerLib.c > > create mode 100644 > > UefiCpuPkg/Library/BaseCpuTimerLib/BaseCpuTimerLib.inf > > create mode 100644 > > UefiCpuPkg/Library/BaseCpuTimerLib/BaseCpuTimerLib.uni > > create mode 100644 UefiCpuPkg/Library/BaseCpuTimerLib/CpuTimerLib.c > > > > diff --git a/UefiCpuPkg/Library/BaseCpuTimerLib/BaseCpuTimerLib.c > > b/UefiCpuPkg/Library/BaseCpuTimerLib/BaseCpuTimerLib.c > > new file mode 100644 > > index 0000000000..ccb92a95d3 > > --- /dev/null > > +++ b/UefiCpuPkg/Library/BaseCpuTimerLib/BaseCpuTimerLib.c > > @@ -0,0 +1,40 @@ > > +/** @file > > + CPUID Leaf 0x15 for Core Crystal Clock frequency instance of Timer > Library. > > + > > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#include > > +#include > > +#include > > + > > +/** > > + CPUID Leaf 0x15 for Core Crystal Clock Frequency. > > + > > + The TSC counting frequency is determined by using CPUID leaf 0x15. > > Frequency in MHz =3D Core XTAL frequency * EBX/EAX. > > + In newer flavors of the CPU, core xtal frequency is returned in ECX > > + or 0 if > > not supported. > > + @return The number of TSC counts per second. > > + > > +**/ > > +UINT64 > > +CpuidCoreClockCalculateTscFrequency ( > > + VOID > > + ); > > + > > +/** > > + Internal function to retrieves the 64-bit frequency in Hz. > > + > > + Internal function to retrieves the 64-bit frequency in Hz. > > + > > + @return The frequency in Hz. > > + > > +**/ > > +UINT64 > > +InternalGetPerformanceCounterFrequency ( > > + VOID > > + ) > > +{ > > + return CpuidCoreClockCalculateTscFrequency (); } > > diff --git a/UefiCpuPkg/Library/BaseCpuTimerLib/BaseCpuTimerLib.inf > > b/UefiCpuPkg/Library/BaseCpuTimerLib/BaseCpuTimerLib.inf > > new file mode 100644 > > index 0000000000..7e27a55c90 > > --- /dev/null > > +++ b/UefiCpuPkg/Library/BaseCpuTimerLib/BaseCpuTimerLib.inf > > @@ -0,0 +1,35 @@ > > +## @file > > +# Base CPU Timer Library > > +# > > +# Provides basic timer support using CPUID Leaf 0x15 XTAL frequency. > > +The performance # counter features are provided by the processors > > +time > > stamp counter. > > +# > > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
# > > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > > + > > +[Defines] > > + INF_VERSION =3D 0x00010005 > > + BASE_NAME =3D BaseCpuTimerLib > > + FILE_GUID =3D F10B5B91-D15A-496C-B044-B5235721A= A08 > > + MODULE_TYPE =3D BASE > > + VERSION_STRING =3D 1.0 > > + LIBRARY_CLASS =3D TimerLib > > + MODULE_UNI_FILE =3D BaseCpuTimerLib.uni > > + > > +[Sources] > > + CpuTimerLib.c > > + BaseCpuTimerLib.c > > + > > +[Packages] > > + MdePkg/MdePkg.dec > > + UefiCpuPkg/UefiCpuPkg.dec > > + > > +[LibraryClasses] > > + BaseLib > > + PcdLib > > + DebugLib > > + > > +[Pcd] > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## > > +CONSUMES > > diff --git a/UefiCpuPkg/Library/BaseCpuTimerLib/BaseCpuTimerLib.uni > > b/UefiCpuPkg/Library/BaseCpuTimerLib/BaseCpuTimerLib.uni > > new file mode 100644 > > index 0000000000..6e5c3ef70e > > --- /dev/null > > +++ b/UefiCpuPkg/Library/BaseCpuTimerLib/BaseCpuTimerLib.uni > > @@ -0,0 +1,16 @@ > > +// /** @file > > +// Base CPU Timer Library > > +// > > +// Provides basic timer support using CPUID Leaf 0x15 XTAL frequency. > > +The performance // counter features are provided by the processors > > +time > > stamp counter. > > +// > > +// Copyright (c) 2019, Intel Corporation. All rights reserved.
// > > +// SPDX-License-Identifier: BSD-2-Clause-Patent // // **/ > > + > > + > > +#string STR_MODULE_ABSTRACT #language en-US "CPU Timer > > Library" > > + > > +#string STR_MODULE_DESCRIPTION #language en-US "Provides > basic > > timer support using CPUID Leaf 0x15 XTAL frequency." > > diff --git a/UefiCpuPkg/Library/BaseCpuTimerLib/CpuTimerLib.c > > b/UefiCpuPkg/Library/BaseCpuTimerLib/CpuTimerLib.c > > new file mode 100644 > > index 0000000000..39492acd8e > > --- /dev/null > > +++ b/UefiCpuPkg/Library/BaseCpuTimerLib/CpuTimerLib.c > > @@ -0,0 +1,272 @@ > > +/** @file > > + CPUID Leaf 0x15 for Core Crystal Clock frequency instance of Timer > Library. > > + > > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/** > > + Internal function to retrieves the 64-bit frequency in Hz. > > + > > + Internal function to retrieves the 64-bit frequency in Hz. > > + > > + @return The frequency in Hz. > > + > > +**/ > > +UINT64 > > +InternalGetPerformanceCounterFrequency ( > > + VOID > > + ); > > + > > +/** > > + CPUID Leaf 0x15 for Core Crystal Clock Frequency. > > + > > + The TSC counting frequency is determined by using CPUID leaf 0x15. > > Frequency in MHz =3D Core XTAL frequency * EBX/EAX. > > + In newer flavors of the CPU, core xtal frequency is returned in ECX > > + or 0 if > > not supported. > > + @return The number of TSC counts per second. > > + > > +**/ > > +UINT64 > > +CpuidCoreClockCalculateTscFrequency ( > > + VOID > > + ) > > +{ > > + CPUID_VERSION_INFO_EAX Eax; > > + UINT64 TscFrequency; > > + UINT64 CoreXtalFrequency; > > + UINT32 RegEax; > > + UINT32 RegEbx; > > + UINT32 RegEcx; > > + > > + // > > + // Use CPUID leaf 0x15 Time Stamp Counter and Nominal Core Crystal > > + Clock Information // EBX returns 0 if not supported. ECX, if non > > + zero, > > provides Core Xtal Frequency in hertz. > > + // TSC frequency =3D (ECX, Core Xtal Frequency) * EBX/EAX. > > + // > > + AsmCpuid (CPUID_TIME_STAMP_COUNTER, &RegEax, &RegEbx, > &RegEcx, > > NULL); > > + > > + // > > + // If EBX returns 0, the XTAL ratio is not enumerated. > > + // > > + ASSERT (RegEbx !=3D 0); > > + // > > + // If ECX returns 0, the XTAL frequency is not enumerated. > > + // > > + if (RegEcx =3D=3D 0) { > > + CoreXtalFrequency =3D PcdGet64 (PcdCpuCoreCrystalClockFrequency); > > + } else { > > + CoreXtalFrequency =3D (UINT64) RegEcx; } > > + > > + // > > + // Calculate TSC frequency =3D (ECX, Core Xtal Frequency) * EBX/EAX > > + // TscFrequency =3D DivU64x32 (MultU64x32 (CoreXtalFrequency, RegEbx) > > + + (UINT64)(RegEax >> 1), RegEax); > > + > > + return TscFrequency; > > +} > > + > > +/** > > + Stalls the CPU for at least the given number of ticks. > > + > > + Stalls the CPU for at least the given number of ticks. It's invoked > > + by > > + MicroSecondDelay() and NanoSecondDelay(). > > + > > + @param Delay A period of time to delay in ticks. > > + > > +**/ > > +VOID > > +InternalCpuDelay ( > > + IN UINT64 Delay > > + ) > > +{ > > + UINT64 Ticks; > > + > > + // > > + // The target timer count is calculated here // Ticks =3D > > + AsmReadTsc() + Delay; > > + > > + // > > + // Wait until time out > > + // Timer wrap-arounds are NOT handled correctly by this function. > > + // Thus, this function must be called within 10 years of reset > > +since > > + // Intel guarantees a minimum of 10 years before the TSC wraps. > > + // > > + while (AsmReadTsc() <=3D Ticks) { > > + CpuPause(); > > + } > > +} > > + > > +/** > > + Stalls the CPU for at least the given number of microseconds. > > + > > + Stalls the CPU for the number of microseconds specified by > MicroSeconds. > > + > > + @param[in] MicroSeconds The minimum number of microseconds to > > delay. > > + > > + @return MicroSeconds > > + > > +**/ > > +UINTN > > +EFIAPI > > +MicroSecondDelay ( > > + IN UINTN MicroSeconds > > + ) > > +{ > > + > > + InternalCpuDelay ( > > + DivU64x32 ( > > + MultU64x64 ( > > + MicroSeconds, > > + CpuidCoreClockCalculateTscFrequency () > > + ), > > + 1000000u > > + ) > > + ); > > + > > + return MicroSeconds; > > +} > > + > > +/** > > + Stalls the CPU for at least the given number of nanoseconds. > > + > > + Stalls the CPU for the number of nanoseconds specified by NanoSecond= s. > > + > > + @param NanoSeconds The minimum number of nanoseconds to delay. > > + > > + @return NanoSeconds > > + > > +**/ > > +UINTN > > +EFIAPI > > +NanoSecondDelay ( > > + IN UINTN NanoSeconds > > + ) > > +{ > > + > > + InternalCpuDelay ( > > + DivU64x32 ( > > + MultU64x64 ( > > + NanoSeconds, > > + CpuidCoreClockCalculateTscFrequency () > > + ), > > + 1000000000u > > + ) > > + ); > > + > > + return NanoSeconds; > > +} > > + > > +/** > > + Retrieves the current value of a 64-bit free running performance cou= nter. > > + > > + Retrieves the current value of a 64-bit free running performance > > + counter. The counter can either count up by 1 or count down by 1. > > + If the physical performance counter counts by a larger increment, > > + then the counter values must be translated. The properties of the > > + counter can be retrieved from GetPerformanceCounterProperties(). > > + > > + @return The current value of the free running performance counter. > > + > > +**/ > > +UINT64 > > +EFIAPI > > +GetPerformanceCounter ( > > + VOID > > + ) > > +{ > > + return AsmReadTsc (); > > +} > > + > > +/** > > + Retrieves the 64-bit frequency in Hz and the range of performance > > +counter > > + values. > > + > > + If StartValue is not NULL, then the value that the performance > > + counter starts with immediately after is it rolls over is returned > > + in StartValue. If EndValue is not NULL, then the value that the > > + performance counter end with immediately before it rolls over is > > + returned in EndValue. The 64-bit frequency of the performance > > + counter in Hz is always returned. If StartValue is less than > > + EndValue, then the performance counter counts up. If StartValue is > > + greater than EndValue, then the performance counter counts down. For > > + example, a 64-bit free running counter that counts up would have a > > + StartValue of > > + 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running > > + counter > > that counts down would have a StartValue of 0xFFFFFF and an EndValue of > 0. > > + > > + @param StartValue The value the performance counter starts with > > + when > > it > > + rolls over. > > + @param EndValue The value that the performance counter ends with > > before > > + it rolls over. > > + > > + @return The frequency in Hz. > > + > > +**/ > > +UINT64 > > +EFIAPI > > +GetPerformanceCounterProperties ( > > + OUT UINT64 *StartValue, OPTIONAL > > + OUT UINT64 *EndValue OPTIONAL > > + ) > > +{ > > + if (StartValue !=3D NULL) { > > + *StartValue =3D 0; > > + } > > + > > + if (EndValue !=3D NULL) { > > + *EndValue =3D 0xffffffffffffffffULL; } return > > + InternalGetPerformanceCounterFrequency (); } > > + > > +/** > > + Converts elapsed ticks of performance counter to time in nanoseconds= . > > + > > + This function converts the elapsed ticks of running performance > > + counter to time value in unit of nanoseconds. > > + > > + @param Ticks The number of elapsed ticks of running performance > > counter. > > + > > + @return The elapsed time in nanoseconds. > > + > > +**/ > > +UINT64 > > +EFIAPI > > +GetTimeInNanoSecond ( > > + IN UINT64 Ticks > > + ) > > +{ > > + UINT64 Frequency; > > + UINT64 NanoSeconds; > > + UINT64 Remainder; > > + INTN Shift; > > + > > + Frequency =3D GetPerformanceCounterProperties (NULL, NULL); > > + > > + // > > + // Ticks > > + // Time =3D --------- x 1,000,000,000 > > + // Frequency > > + // > > + NanoSeconds =3D MultU64x32 (DivU64x64Remainder (Ticks, Frequency, > > + &Remainder), 1000000000u); > > + > > + // > > + // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit. > > + // Since 2^29 < 1,000,000,000 =3D 0x3B9ACA00 < 2^30, Remainder shoul= d > > + < > > + 2^(64-30) =3D 2^34, // i.e. highest bit set in Remainder should <=3D= 33. > > + // > > + Shift =3D MAX (0, HighBitSet64 (Remainder) - 33); Remainder =3D > > + RShiftU64 (Remainder, (UINTN) Shift); Frequency =3D RShiftU64 > > + (Frequency, (UINTN) Shift); NanoSeconds +=3D DivU64x64Remainder > > + (MultU64x32 (Remainder, 1000000000u), Frequency, NULL); > > + > > + return NanoSeconds; > > +} > > diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec > > index 14ddaa8633..a94bd2ea30 100644 > > --- a/UefiCpuPkg/UefiCpuPkg.dec > > +++ b/UefiCpuPkg/UefiCpuPkg.dec > > @@ -211,6 +211,14 @@ > > # @Prompt If CPU features will be initialized during S3 resume. > > > > gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOO > > LEAN|0x0000001D > > > > + ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core > > Crystal Clock Frequency. > > + # TSC Frequency =3D ECX (core crystal clock frequency) * EBX/EAX. > > + # Intel Xeon Processor Scalable Family with CPUID signature 06_55H= =3D > > 25000000 (25MHz) > > + # 6th and 7th generation Intel Core processors and Intel Xeon W > > Processor Family =3D 24000000 (24MHz) > > + # Intel Atom processors based on Goldmont Microarchitecture with > > CPUID signature 06_5CH =3D 19200000 (19.2MHz) > > + # @Prompt Core Crystal Clock Frequency is for CPUID Leaf 0x15.ECX > > + > > + > > > gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000| > > UIN > > + T64|0x32132113 > > + > > [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] > > ## Specifies max supported number of Logical Processors. > > # @Prompt Configure max supported number of Logical Processors diff > > --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index > > bf690d3978..e1337c741b 100644 > > --- a/UefiCpuPkg/UefiCpuPkg.dsc > > +++ b/UefiCpuPkg/UefiCpuPkg.dsc > > @@ -143,6 +143,7 @@ > > > > SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFea > > turesLibStm.inf > > } > > UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf > > + UefiCpuPkg/Library/BaseCpuTimerLib/BaseCpuTimerLib.inf > > > > [BuildOptions] > > *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES > > -- > > 2.14.2.windows.3