From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 79DF71A1E5E for ; Wed, 21 Sep 2016 01:08:45 -0700 (PDT) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP; 21 Sep 2016 01:08:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,372,1470726000"; d="scan'208";a="11556627" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga006.fm.intel.com with ESMTP; 21 Sep 2016 01:08:44 -0700 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 21 Sep 2016 01:08:44 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx115.amr.corp.intel.com (10.18.116.19) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 21 Sep 2016 01:08:41 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.15]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.118]) with mapi id 14.03.0248.002; Wed, 21 Sep 2016 16:06:44 +0800 From: "Zhang, Chao B" To: "Zeng, Star" , "edk2-devel@lists.01.org" CC: "Yao, Jiewen" Thread-Topic: [PATCH] SecurityPkg/TPM2: Sync PcrAllocations and PcrMask Thread-Index: AQHSEy2TuLte/K6Oq0a2PKw6rOZXUqCDl70g Date: Wed, 21 Sep 2016 08:06:44 +0000 Message-ID: References: <1474368956-184100-1-git-send-email-star.zeng@intel.com> In-Reply-To: <1474368956-184100-1-git-send-email-star.zeng@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_IC x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOWUzN2MzYzctZGVhNC00ZTk0LTlhM2QtMjU1YTE0NGI2ZWQwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IldHOVF6aHFQQlN1MWZZRFFXQW1cLzhYK042dW05cXliYXZnbmU3WjB3K2VrPSJ9 x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] SecurityPkg/TPM2: Sync PcrAllocations and PcrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Sep 2016 08:08:45 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chao Zhang Thanks & Best regards Chao Zhang -----Original Message----- From: Zeng, Star=20 Sent: Tuesday, September 20, 2016 6:56 PM To: edk2-devel@lists.01.org Cc: Yao, Jiewen; Zhang, Chao B Subject: [PATCH] SecurityPkg/TPM2: Sync PcrAllocations and PcrMask From: Jiewen Yao Current TCG2 implementation will set Tpm2HashMask PCD value according to TP= M2 PCR bank. However, there might be misconfiguration in BIOS build phase. The enhanced logic makes sure that the current PCR allocations, the TPM supported PCRs, and the PcdTpm2HashMask are all in agreement. Cc: Chao B Zhang Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Star Zeng --- SecurityPkg/SecurityPkg.dsc | 1 + SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c | 111 +++++++++++++++++++++-----------= ---- SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf | 3 +- 3 files changed, 69 insertions(+), 46 deletions(-) diff --git a/SecurityPkg/SecurityPkg.dsc b/SecurityPkg/SecurityPkg.dsc index 3b36d0f5a77a..2ebd0a432124 100644 --- a/SecurityPkg/SecurityPkg.dsc +++ b/SecurityPkg/SecurityPkg.dsc @@ -74,6 +74,7 @@ [LibraryClasses] TcgStorageCoreLib|SecurityPkg/Library/TcgStorageCoreLib/TcgStorageCoreLi= b.inf TcgStorageOpalLib|SecurityPkg/Library/TcgStorageOpalLib/TcgStorageOpalLi= b.inf OpalPasswordSupportLib|SecurityPkg/Library/OpalPasswordSupportLib/OpalPa= sswordSupportLib.inf + ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseResetSyst= emLibNull.inf =20 [LibraryClasses.common.PEIM] PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf diff --git a/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c b/SecurityPkg/Tcg/Tcg2Pei/Tc= g2Pei.c index a72b8d9bda1f..8bd5f2cfa507 100644 --- a/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c +++ b/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c @@ -41,6 +41,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. #include #include #include +#include #include =20 #define PERF_ID_TCG2_PEI 0x3080 @@ -190,60 +191,80 @@ EndofPeiSignalNotifyCallBack ( } =20 /** - Set Tpm2HashMask PCD value according to TPM2 PCR bank. + Make sure that the current PCR allocations, the TPM supported PCRs, + and the PcdTpm2HashMask are all in agreement. **/ VOID -SetTpm2HashMask ( +SyncPcrAllocationsAndPcrMask ( VOID ) { - EFI_STATUS Status; - UINT32 ActivePcrBanks; - TPML_PCR_SELECTION Pcrs; - UINTN Index; + EFI_STATUS Status; + EFI_TCG2_EVENT_ALGORITHM_BITMAP TpmHashAlgorithmBitmap; + UINT32 TpmActivePcrBanks; + UINT32 NewTpmActivePcrBanks; + UINT32 Tpm2PcrMask; + UINT32 NewTpm2PcrMask; =20 - DEBUG ((EFI_D_ERROR, "SetTpm2HashMask!\n")); + DEBUG ((EFI_D_ERROR, "SyncPcrAllocationsAndPcrMask!\n")); =20 - Status =3D Tpm2GetCapabilityPcrs (&Pcrs); - if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "Tpm2GetCapabilityPcrs fail!\n")); - ActivePcrBanks =3D EFI_TCG2_BOOT_HASH_ALG_SHA1; - } else { - DEBUG ((EFI_D_INFO, "Tpm2GetCapabilityPcrs Count - %08x\n", Pcrs.count= )); - ActivePcrBanks =3D 0; - for (Index =3D 0; Index < Pcrs.count; Index++) { - DEBUG ((EFI_D_INFO, "hash - %x\n", Pcrs.pcrSelections[Index].hash)); - switch (Pcrs.pcrSelections[Index].hash) { - case TPM_ALG_SHA1: - if (!IsZeroBuffer (Pcrs.pcrSelections[Index].pcrSelect, Pcrs.pcrSe= lections[Index].sizeofSelect)) { - ActivePcrBanks |=3D EFI_TCG2_BOOT_HASH_ALG_SHA1; - } =20 - break; - case TPM_ALG_SHA256: - if (!IsZeroBuffer (Pcrs.pcrSelections[Index].pcrSelect, Pcrs.pcrSe= lections[Index].sizeofSelect)) { - ActivePcrBanks |=3D EFI_TCG2_BOOT_HASH_ALG_SHA256; - } - break; - case TPM_ALG_SHA384: - if (!IsZeroBuffer (Pcrs.pcrSelections[Index].pcrSelect, Pcrs.pcrSe= lections[Index].sizeofSelect)) { - ActivePcrBanks |=3D EFI_TCG2_BOOT_HASH_ALG_SHA384; - } - break; - case TPM_ALG_SHA512: - if (!IsZeroBuffer (Pcrs.pcrSelections[Index].pcrSelect, Pcrs.pcrSe= lections[Index].sizeofSelect)) { - ActivePcrBanks |=3D EFI_TCG2_BOOT_HASH_ALG_SHA512; - } - break; - case TPM_ALG_SM3_256: - if (!IsZeroBuffer (Pcrs.pcrSelections[Index].pcrSelect, Pcrs.pcrSe= lections[Index].sizeofSelect)) { - ActivePcrBanks |=3D EFI_TCG2_BOOT_HASH_ALG_SM3_256; - } - break; + // + // Determine the current TPM support and the Platform PCR mask. + // + Status =3D Tpm2GetCapabilitySupportedAndActivePcrs (&TpmHashAlgorithmBit= map, &TpmActivePcrBanks); + ASSERT_EFI_ERROR (Status); + + Tpm2PcrMask =3D PcdGet32 (PcdTpm2HashMask); + + // + // Find the intersection of Pcd support and TPM support. + // If banks are missing from the TPM support that are in the PCD, update= the PCD. + // If banks are missing from the PCD that are active in the TPM, realloc= ate the banks and reboot. + // + + // + // If there are active PCR banks that are not supported by the Platform = mask, + // update the TPM allocations and reboot the machine. + // + if ((TpmActivePcrBanks & Tpm2PcrMask) !=3D TpmActivePcrBanks) { + NewTpmActivePcrBanks =3D TpmActivePcrBanks & Tpm2PcrMask; + + DEBUG ((EFI_D_INFO, __FUNCTION__" - Reallocating PCR banks from 0x%X t= o 0x%X.\n", TpmActivePcrBanks, NewTpmActivePcrBanks )); + if (NewTpmActivePcrBanks =3D=3D 0) { + DEBUG ((EFI_D_ERROR, __FUNCTION__" - No viable PCRs active! Please s= et a less restrictive value for PcdTpm2HashMask!\n")); + ASSERT (FALSE); + } else { + Status =3D Tpm2PcrAllocateBanks (NULL, (UINT32)TpmHashAlgorithmBitma= p, NewTpmActivePcrBanks); + if (EFI_ERROR (Status)) { + // + // We can't do much here, but we hope that this doesn't happen. + // + DEBUG ((EFI_D_ERROR, __FUNCTION__" - Failed to reallocate PCRs!\n"= )); + ASSERT_EFI_ERROR (Status); } + // + // Need reset system, since we just called Tpm2PcrAllocateBanks(). + // + ResetCold(); } } - Status =3D PcdSet32S (PcdTpm2HashMask, ActivePcrBanks); - ASSERT_EFI_ERROR (Status); + + // + // If there are any PCRs that claim support in the Platform mask that ar= e + // not supported by the TPM, update the mask. + // + if ((Tpm2PcrMask & TpmHashAlgorithmBitmap) !=3D Tpm2PcrMask) { + NewTpm2PcrMask =3D Tpm2PcrMask & TpmHashAlgorithmBitmap; + + DEBUG ((EFI_D_INFO, __FUNCTION__" - Updating PcdTpm2HashMask from 0x%X= to 0x%X.\n", Tpm2PcrMask, NewTpm2PcrMask )); + if (NewTpm2PcrMask =3D=3D 0) { + DEBUG ((EFI_D_ERROR, __FUNCTION__" - No viable PCRs supported! Pleas= e set a less restrictive value for PcdTpm2HashMask!\n")); + ASSERT (FALSE); + } + + Status =3D PcdSet32S (PcdTpm2HashMask, NewTpm2PcrMask); + ASSERT_EFI_ERROR (Status); + } } =20 /** @@ -767,7 +788,7 @@ PeimEntryMA ( // // Update Tpm2HashMask according to PCR bank. // - SetTpm2HashMask (); + SyncPcrAllocationsAndPcrMask (); =20 if (S3ErrorReport) { // diff --git a/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf b/SecurityPkg/Tcg/Tcg2Pei/= Tcg2Pei.inf index 007ce918eda9..3477d8206a8b 100644 --- a/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf +++ b/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf @@ -3,7 +3,7 @@ # # This module will initialize TPM device, measure reported FVs and BIOS v= ersion. # -# Copyright (c) 2015, Intel Corporation. All rights reserved.
+# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
# This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may be= found at @@ -53,6 +53,7 @@ [LibraryClasses] MemoryAllocationLib ReportStatusCodeLib Tcg2PhysicalPresenceLib + ResetSystemLib =20 [Guids] gTcgEventEntryHobGuid ## = PRODUCES ## HOB --=20 2.7.0.windows.1