From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Permerror (SPF Permanent Error: More than 10 MX records returned) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=chao.b.zhang@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7FC38221EA0A5 for ; Thu, 7 Dec 2017 18:18:26 -0800 (PST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Dec 2017 18:22:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,375,1508828400"; d="scan'208";a="185135115" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga006.fm.intel.com with ESMTP; 07 Dec 2017 18:22:58 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 7 Dec 2017 18:22:55 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.175]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Fri, 8 Dec 2017 10:22:18 +0800 From: "Zhang, Chao B" To: "Yao, Jiewen" , "edk2-devel@lists.01.org" CC: "Long, Qin" Thread-Topic: [edk2] [PATCH] SecurityPkg:Tcg2Smm:Enabling TPM SIRQ interrupt support Thread-Index: AQHTb73AlrRES3xn+kG2MChk3zRK7qM4IDQAgACUAhA= Date: Fri, 8 Dec 2017 02:22:17 +0000 Message-ID: References: <20171208004434.50468-1-chao.b.zhang@intel.com> <74D8A39837DF1E4DA445A8C0B3885C503AA3E67C@shsmsx102.ccr.corp.intel.com> In-Reply-To: <74D8A39837DF1E4DA445A8C0B3885C503AA3E67C@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_IC x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTk3NjMwNGMtM2ZmZC00ZDJhLWFiOTYtYWY5ZjU0NzdkNDYxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJSQTZJUVhNSmRyd1hcL1lYNHRGb1gzMnUwbGVtXC80c2dlOFNXc1NEN2lZVGlEXC9FR1FUZTVcL0RDUFZPTnpHb3NDNiJ9 dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] SecurityPkg:Tcg2Smm:Enabling TPM SIRQ interrupt support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Dec 2017 02:18:26 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Jiewen & All: We verified Infineon(TIS + LPC, TIS +SPI) & Nuvoton(CRB+SPI, FIFO +LPC)= TPM2.0 chip on Intel Kabylake Platform. TPM can work well both in boot & = OS phase. -----Original Message----- From: Yao, Jiewen=20 Sent: Friday, December 8, 2017 9:22 AM To: Zhang, Chao B ; edk2-devel@lists.01.org Cc: Zhang, Chao B ; Long, Qin Subject: RE: [edk2] [PATCH] SecurityPkg:Tcg2Smm:Enabling TPM SIRQ interrupt= support Thanks. Would you please also provide the information on what platform and TPM chip= we have validated? Reviewed-by: Jiewen.yao@intel.com Thank you Yao Jiewen > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of=20 > Zhang, Chao B > Sent: Friday, December 8, 2017 8:45 AM > To: edk2-devel@lists.01.org > Cc: Yao, Jiewen ; Zhang, Chao B=20 > ; Long, Qin > Subject: [edk2] [PATCH] SecurityPkg:Tcg2Smm:Enabling TPM SIRQ=20 > interrupt support >=20 > 1. Report TPM SIRQ interrupt resource through _CRS 2. Expose _SRS to=20 > update interrupt resource & FIFO/TIS interrupt related registers > defined in TCG PC Client Platform TPM Profile (PTP) Specification=20 > spec=20 > https://trustedcomputinggroup.org/wp-content/uploads/PC-Client-Specifi > c-Platf orm-TPM-Profile-for-TPM-2-0-v43-150126.pdf > Note: IHV/OEM need to carefully verify this feature with OS TPM driver=20 > to make sure there is no impact to system/HW >=20 > Cc: Long Qin > Cc: Jiewen Yao > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Chao Zhang > --- > SecurityPkg/Tcg/Tcg2Smm/Tpm.asl | 112 > +++++++++++++++++++++++++++++++++++++--- > 1 file changed, 104 insertions(+), 8 deletions(-) >=20 > diff --git a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl=20 > b/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl index cf0642e..68b5073 100644 > --- a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl > +++ b/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl > @@ -44,13 +44,6 @@ DefinitionBlock ( > Name (_STR, Unicode ("TPM 2.0 Device")) >=20 > // > - // Return the resource consumed by TPM device > - // > - Name (_CRS, ResourceTemplate () { > - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) > - }) > - > - // > // Operational region for Smi port access > // > OperationRegion (SMIP, SystemIO, 0xB2, 1) @@ -65,7 +58,19 @@=20 > DefinitionBlock ( > OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000) > Field (TPMR, AnyAcc, NoLock, Preserve) > { > - ACC0, 8, > + ACC0, 8, // TPM_ACCESS_0 > + Offset(0x8), > + INTE, 32, // TPM_INT_ENABLE_0 > + INTV, 8, // TPM_INT_VECTOR_0 > + Offset(0x10), > + INTS, 32, // TPM_INT_STATUS_0 > + INTF, 32, // TPM_INTF_CAPABILITY_0 > + STS0, 32, // TPM_STS_0 > + Offset(0x24), > + FIFO, 32, // TPM_DATA_FIFO_0 > + Offset(0x30), > + TID0, 32, // TPM_INTERFACE_ID_0 > + // ignore the rest > } >=20 > // > @@ -89,6 +94,97 @@ DefinitionBlock ( > UCRQ, 32 // Phyical Presence request operation to Get User > Confirmation Status > } >=20 > + Name(RESO, ResourceTemplate () { > + Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REGS) > + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) {= 12} > + }) > + > + // > + // Return the resource consumed by TPM device. > + // > + Method(_CRS,0,Serialized) > + { > + Return(RESO) > + } > + > + // > + // Set resources consumed by the TPM device. This is used to > + // assign an interrupt number to the device. The input byte stream > + // has to be the same as returned by _CRS (according to ACPI spec)= . > + // > + Method(_SRS,1,Serialized) > + { > + // > + // Update resource descriptor > + // Use the field name to identify the offsets in the argument > + // buffer and RESO buffer. > + // > + CreateDWordField(Arg0, ^IRQ._INT, IRQ0) > + CreateDWordField(RESO, ^IRQ._INT, LIRQ) > + Store(IRQ0, LIRQ) > + > + CreateBitField(Arg0, ^IRQ._HE, ITRG) > + CreateBitField(RESO, ^IRQ._HE, LTRG) > + Store(ITRG, LTRG) > + > + CreateBitField(Arg0, ^IRQ._LL, ILVL) > + CreateBitField(RESO, ^IRQ._LL, LLVL) > + Store(ILVL, LLVL) > + > + // > + // Update TPM FIFO PTP/TIS interface only, identified by > TPM_INTERFACE_ID_x lowest > + // nibble. > + // 0000 - FIFO interface as defined in PTP for TPM 2.0 is active > + // 1111 - FIFO interface as defined in TIS1.3 is active > + // > + If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0,=20 > + 0x0F), > 0x0F))) { > + // > + // If FIFO interface, interrupt vector register is > + // available. TCG PTP specification allows only > + // values 1..15 in this field. For other interrupts > + // the field should stay 0. > + // > + If (LLess (IRQ0, 16)) { > + Store (And(IRQ0, 0xF), INTV) > + } > + // > + // Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4 > + // contains settings for interrupt polarity. > + // The other bits of the byte enable individual interrupts. > + // They should be all be zero, but to avoid changing the > + // configuration, the other bits are be preserved. > + // 00 - high level > + // 01 - low level > + // 10 - rising edge > + // 11 - falling edge > + // > + // ACPI spec definitions: > + // _HE: '1' is Edge, '0' is Level > + // _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG= spec) > + // > + If (LEqual (ITRG, 1)) { > + Or(INTE, 0x00000010, INTE) > + } Else { > + And(INTE, 0xFFFFFFEF, INTE) > + } > + if (LEqual (ILVL, 0)) { > + Or(INTE, 0x00000008, INTE) > + } Else { > + And(INTE, 0xFFFFFFF7, INTE) > + } > + } > + } > + > + // > + // Possible resource settings. > + // The format of the data has to follow the same format as > + // _CRS (according to ACPI spec). > + // > + Name (_PRS, ResourceTemplate() { > + Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) > + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,=20 > + SIRQ) > {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15} > + }) > + > Method (PTS, 1, Serialized) > { > // > -- > 1.9.5.msysgit.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel