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LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Jul 2017 17:06:43.5773 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0801MB1444 X-Content-Filtered-By: Mailman/MimeDel 2.1.22 Subject: Re: [PATCH 2/2] BaseTools/tools_def AARCH64: avoid SIMD register in XIP code X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 13 Jul 2017 17:05:02 -0000 Content-Language: en-GB Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable -mgeneral-regs-only is already there: See the top of generated .S file: .arch armv8-a .file "" // GNU GIMPLE (Linaro GCC 7.1-2017.05) version 7.1.1 20170510 (aarch64-elf) // compiled by GNU C version 4.8.2, GMP version 6.1.2, MPFR version 3.1.= 5, MPC version 1.0.3, isl version none // GGC heuristics: --param ggc-min-expand=3D100 --param ggc-min-heapsize=3D= 131072 // options passed: -mlittle-endian -mcmodel=3Dtiny -march=3Darmv8-a -mabi= =3Dlp64 // -mstrict-align -mgeneral-regs-only -mlittle-endian -mcmodel=3Dtiny // -march=3Darmv8-a -mabi=3Dlp64 // -auxbase-strip ArmVeNorFlashDxe.dll.ltrans0.ltrans.o -g -g -O3 -O3 -Os // -Os -O3 -Wno-lto-type-mismatch -Wno-array-bounds ________________________________ From: Ard Biesheuvel Sent: 13 July 2017 18:00:43 To: Alexei Fedorov Cc: Leif Lindholm; edk2-devel@lists.01.org; liming.gao@intel.com; yonghong.= zhu@intel.com; Evan Lloyd Subject: Re: [PATCH 2/2] BaseTools/tools_def AARCH64: avoid SIMD register i= n XIP code On 13 July 2017 at 17:56, Alexei Fedorov wrote: > I'm getting > > > UEFI firmware (version built at 16:34:57 on Jul 13 2017) > Synchronous Exception at 0x00000000F5451338 > : > > EL2:0x00000000F5451338 : LDR q0,[x9,x0] > EL2:0x00000000F545133C : ADD x1,x1,#1 > EL2:0x00000000F5451340 : CMP x7,x1 > EL2:0x00000000F5451344 : STR q0,[x2,x0] > EL2:0x00000000F5451348 : ADD x0,x0,#0x10 > EL2:0x00000000F545134C : B.HI {pc}-0x14 ; 0xf5451338 > ... > > with X0=3D0 & X9 =3D 0x000000000BFD0008 (Flash memory) in AlignedCopyMem(= ) > function > > (edk2\ArmPlatformPkg\Drivers\NorFlashDxe\NorFlashDxe.c): > > > // r:\edk2\ArmPlatformPkg\Drivers\NorFlashDxe\NorFlashDxe.c:784: > *Destination64++ =3D *Source64++; > .loc 10 784 0 > ldr q0, [x9, x0] // MEM[base: vectp.229_593, index: > ivtmp.349_1117, offset: 0B], MEM[base: vectp.229_593, index: ivtmp.349_11= 17, > offset: 0B] > add x1, x1, 1 // ivtmp_603, ivtmp_603, > cmp x7, x1 // bnd.223, ivtmp_603 > str q0, [x2, x0] // MEM[base: vectp.229_593, index: > ivtmp.349_1117, offset: 0B], MEM[base: vectp_Buffer.232_598, index: > ivtmp.349_1117, offset: 0B] > add x0, x0, 16 // ivtmp.349, ivtmp.349, > bhi .L200 //, > > > Despite compiler option -mgeneral-regs-only: > > // -mfix-cortex-a53-835769 -mfix-cortex-a53-843419 -mgeneral-regs-only > // -mlittle-endian -mpc-relative-literal-loads -mstrict-align > (see attached assembly generated file) > That is the same compiler bug at work, I think. So we need to add -mgeneral-regs-only for this module as well. Perhaps we should simply set it globally? Leif? IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. If you are not the intended recipient, p= lease notify the sender immediately and do not disclose the contents to any= other person, use it for any purpose, or store or copy the information in = any medium. Thank you.