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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,vivek.kasireddy@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: lO4QTLcabJYmb28ngiYo8JEmx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=ZYtPxTQC; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Hi Gerd, >=20 > Hi, >=20 > > > I agree that the proposed patch can function as a stop-gap, but the Q= EMU > > > command line hack is already a stop-gap. And for the long term, this > > > patch is not good enough. We should enhance the dynamic sizing, now > that > > > Gerd has put it into place. > > > > ... I do agree however that the current behavior is strange -- the user > > specifies an explicit fw_cfg knob for OVMF, and OVMF ignores it (for > > whatever reason). > > > > I'd like to know what Gerd thinks of this. >=20 > The current code effectively considers the user-specified PciMmio64Size > as a lower limit, it will never be smaller but might be larger in case > OVMF figures it has enough space. >=20 > Being more strict here and use the user-specified PciMmio64Size as-is no > matter what is fine with me. >=20 > The independent but related question is where the window should be > placed in case we have a valid vcpu address space size and PciMmio64Size > specified by the user. >=20 > > (b) there were a promise to enhance QEMU and OVMF as I suggest above. >=20 > Fully agree. We should explicitly communicate requirements (in this > case: iommu address space size) instead of depending on side effects > of unrelated config options. >=20 > Strictly speaking you don't care that much about the size of the mmio > window, but where it gets placed. Moving it to the end of the vcpu > address space is what breaks your use case in case the iommu address > space happens to be too small for that. Right, the crux of the problem is indeed the placement of the window and not the size. Given this, do you see any problem if the mmio window were to be placed at the lower end of the address space? Or, do you think ensuring that PhysMemAddressWidth =3D automatically via Qemu/OVMF like Laszlo suggested is a better solution for this problem? Thanks, Vivek >=20 > take care, > Gerd -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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