From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 27A88D8100D for ; Tue, 23 Jan 2024 10:44:40 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=EBgXYI47BG2mM24nL7sHeSFTXXga20+kwxRPu6qP2UY=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:msip_labels:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1706006679; v=1; b=wfFetMBR/33q3tfWXOufKOmfBo6ZvaTipxyRaSWzyFa5c3oZaEM3JM8hTTpr4cq28n9ZL20I ak2h6wYTmNzbDSIND+qPGUrnawFrHwFdKUWwsNcV4H1Bs+hXVCFJxyubE3aJQ64GXaYDtoCBJkJ /N3TwRryn9H6UBP5dMI30BR0= X-Received: by 127.0.0.2 with SMTP id Gm9xYY7687511xCEF2ZsR0CZ; Tue, 23 Jan 2024 02:44:39 -0800 X-Received: from NAM04-DM6-obe.outbound.protection.outlook.com (NAM04-DM6-obe.outbound.protection.outlook.com [40.107.102.52]) by mx.groups.io with SMTP id smtpd.web10.9233.1706006679001401474 for ; Tue, 23 Jan 2024 02:44:39 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HWXshqiOxIiBg8GI6iMWKLq6Rt1IRBOa91rYSWLD6q5ElZ81vRE8s4I6uxZUUU1tobFzM6U03KY8sIEnJZ1yOUNYNTyHnhge7x435paj57S6A3Gg/D00QJOI1Wj4lov/TRLlkpK10sWtW2N+WCAJkDT/Fd79z/mRNRQvwdVvdmn3YWKv492pO+wWG+IQ/gaRaNm/qKY8uTbDVYiJ+mpoRvMONE4V61ySmO7VV9Jf9KuDEBwbB7joMm3T+23C3hkv3rHc7TU/Qok9IloK+W0gEGikjqd/2Z/TDQXdM09XceGz1CUa71Gguf/U42fzKbhz//g4rL0twgVHmjI5ez9/oA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=b5LWKbH+UST07s14QSeI7RoW9v1qDPTVjUcj/q5GwAQ=; b=il9W+2VR0UM5TDEGIcmmLT10x6/wLS06XILKt58R65eBl1xE1hZrj9gyvXyI+G8agGQJZ0XCSfAqcuVc8VGdVtgiwZMbFoJQQdK+u+t6ugX0/P1w+ISeErT4rn7HXARQ0ItFMvswp/i6Bl8bih/yvk7HxEwfHJoqEZxKZ7hXRva0wds1hIAIEA1eONwwgik/ts6n5EOYVq5fftFc2SBIueFSw5QAJcrQXqSIY3REMSDF+wUxCvjQ25arxGILQoW8Vbk4o3tGlVPPV7cTOTy7kxDw3cXlLabjPHqUMvAZhZz9fe7r9uwqCPNi06ALvDp3HuT3r06hacUCCNHqgkwASQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from LV8PR12MB9452.namprd12.prod.outlook.com (2603:10b6:408:200::8) by CH3PR12MB8332.namprd12.prod.outlook.com (2603:10b6:610:131::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7202.34; Tue, 23 Jan 2024 10:44:35 +0000 X-Received: from LV8PR12MB9452.namprd12.prod.outlook.com ([fe80::67bd:f1b9:58a3:d2e6]) by LV8PR12MB9452.namprd12.prod.outlook.com ([fe80::67bd:f1b9:58a3:d2e6%7]) with mapi id 15.20.7202.031; Tue, 23 Jan 2024 10:44:35 +0000 From: "Chang, Abner via groups.io" To: "Xing, Eric" , "Attar, AbdulLateef (Abdul Lateef)" , "devel@edk2.groups.io" , "Zhai, MingXin (Duke)" CC: "Fu, Igniculus" Subject: Re: [edk2-devel] [PATCH 29/33] AMD/VanGoghBoard: Check in SmramSaveState module. Thread-Topic: [edk2-devel] [PATCH 29/33] AMD/VanGoghBoard: Check in SmramSaveState module. Thread-Index: AQHaSdsMrnd3RTAD8EGxV8WCH01fzbDiyMYAgAQZq0CAAFduAIAABKEg Date: Tue, 23 Jan 2024 10:44:35 +0000 Message-ID: References: <20240118065046.961-1-duke.zhai@amd.com> <20240118065046.961-30-duke.zhai@amd.com> In-Reply-To: Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_ActionId=02838958-029d-4961-8220-a70b67dc0815;MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_ContentBits=0;MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_Enabled=true;MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_Method=Standard;MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_Name=General;MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_SetDate=2024-01-20T14:35:46Z;MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_SiteId=3dd8961f-e488-4e60-8e11-a82d994e183d; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: LV8PR12MB9452:EE_|CH3PR12MB8332:EE_ x-ms-office365-filtering-correlation-id: f3e0b61f-1f35-4192-cd43-08dc1c004a79 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: AJLxIKfvRJMld6yQOM2kL+T5jlJqp3I3yCdl8uxhPBm3ARq2I/ROsOCGieDRDOf6rX6//jm7bbuIqt+tCeKsXwpivmvHPR2STqkFslql1TidBarm+gRh9ikSRJsx03o/Bshxnb4+sDTEfIJnzHEOpHomTK3ySAFA+UYk8lkg45TpHaU4kpdB7ADmB7ILM0FGekh5K53V4eYRTjp2gAOTy190A2PD6DlNsy4nSY21FC37X4vv1vulLq5E7YmzoOrJFAgri1LPVdp+WXV1naSmyW8uoirfLS71pzC5HcVL1PCFihUUR/Hby/gWCDMhkftK5y4qw2T/7kFGAuhv9Ac67sZtWAzlXPNP/B9NXPMU5pB8a9JiSMLTAo5QeE7P/VK9M84DmRQpxR090oMULPRvhjoNdWrtmKtmQTNX2xcraJJtdK77y7q88Y2AMgoEFsIhdYJGOoK9USdcZTDJZhaEWLLibdlDZzyBoI8OQKtbd771b/jChSvVXJQsXHy/xhD5UeNs+clsucl+3RytKrxtPGP9LhRrrpowGi1upNt6EeJ87b+zccGqS5iXshiv0jkHsZPdxrL0T3pyVyBaJEQVTtTpcrHYODiqFJqjSfAcqG6WRoYVKi81VJsiDzFi7lJ6SXQ/6UWIKqD0Ovo8/0rvcg== x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?HUb8MN+ZnWRj3OGyDUD5tCH5wXL7kPYA4/DfkuRAkF+sMguz82hJE9ZyzzEu?= =?us-ascii?Q?67ke/K2U0sqcPbYPs+7ccMg4H4EUmNNkig3pmyEJ5UseVmMR34O3UmWVGQxH?= =?us-ascii?Q?biZz6Etiu9a1XoBji603YcwPVzpACfIUZnsH4lcCYWPTEdo8Dcv2H3LE8417?= =?us-ascii?Q?6jn2rLwczHl33w2udhZ0yDtZUZzP716TCFOhRNbvi1gMff38x3O078BsARnb?= =?us-ascii?Q?6BaIUc6AVfkxKp07i2886v92mWlNLTig+PTeau/MwTFfW3SwXFbgpq/ric3N?= =?us-ascii?Q?FPD5TbpDM5S3soX80Mi+idBNhByytSLNtDcxEPf53VvadkUc1fwHMwPoGBeN?= =?us-ascii?Q?D0lMnwFSUuA4wvksJGBRS9Cf3FgAWOpPkBY93z9m1DS1YNbHjN9+Mb3X7AOq?= =?us-ascii?Q?KkBf+Zs3gXp4HszsYsx6jLrxA3tPk7uI6535QlswcgE3fs5LAfn/+/jNdNib?= =?us-ascii?Q?jxWuhpLt54mEC63KuXE5jZB7eQqr26PhJSi4I0/RsPSVDTjCHiS4KT6t276l?= =?us-ascii?Q?I9cK3vq530bekdELsdRFOHQWQboWs4Drcni2gWaanXP9cEQHe6sVOySdn3zO?= =?us-ascii?Q?wlNZCdiNLeTFTxnwg1f+ipGD22evyeDj5DAom1cwHuE+WOKJ0SBbFV1/3QAv?= =?us-ascii?Q?LNhnwHBK7CHs27Z3VpnmsMHelShyYemtQ6Ej6M0h7DMytmMhmPZzB/EuylXm?= =?us-ascii?Q?ccSCqlIcZ9dQRqvnhN2No99waNcG+PbxzmiRAcPXSMpz9UgrDSY0xCcsoMld?= =?us-ascii?Q?30DhbLlhRK9SF1XMmVCLZCR7AwSdYigprLPHIlrfC20ElPjnt6LrbsJJNlQI?= =?us-ascii?Q?gTq/ENV5SGl18Gmg5S8/4KpUd0CxHpZT3MZ869bymi9o2kXAA+FM5/qUNUAF?= =?us-ascii?Q?CpAAF8L+Ru2SNdh3VWb79cOr+OOUeV7/1vIs8lQtwvwFqG/c9HHXl4djqkQL?= =?us-ascii?Q?KDsqtnFnH47RK8G4K4lhCFYp1Rb4AsNI4TTJJFGOF2leXh+i1ZZ0pjdA/Uf1?= =?us-ascii?Q?DLAtUEMPymGcdmWnApzOZCBPh5XDU+qfrddoGa4cDlACgSS1Bv18K+1qdZK9?= =?us-ascii?Q?st1pU60XXhVoBNSfZnw9nxWVf0DzCtF9NH75R+K8FTkDMIrk0hlCc+vp15ir?= =?us-ascii?Q?V7Pyl7/2CVQdwC+aywVVH+lanLUxcfyfQsCrjSadlfMSAg0lqnNaCde5apa8?= =?us-ascii?Q?AAOvQvH+yKaI1WB66bCyxg0j8Lc+Nqe30NCTLGCibtH+/MHYDgk3lnSCLuT6?= =?us-ascii?Q?DZsGTENOjUajyJLYhPdupR50kf5LbuwTk8tJOuGzS3HFSO/IuYbWYSbpCB7f?= =?us-ascii?Q?s0RV2T8riBBUMQoK0tvmybD2dzNOYj/N+W5u0hrLxNi/wxn3GGOzf9PKBPRz?= =?us-ascii?Q?NIwB+5KkMJE2igJgIJGAVkzutI7DwOGxlFWccVY99SgPzxrkJw6FctCrwH2K?= =?us-ascii?Q?2L/o0V5NwOZX2m30To4loeTqU8gaZDIOl8nL1W1SJJtE+CHxSwJl9UDgkQnI?= =?us-ascii?Q?dtzBiLzGqLDbzaBE2nmCHC9ZwnfszkivLP4P575IGMXgwKgqJSsZHCZXpSB1?= =?us-ascii?Q?575wNK9q2LREVOLyYeBVHYkf4R8rTrj7xoOFFTrQ?= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: LV8PR12MB9452.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f3e0b61f-1f35-4192-cd43-08dc1c004a79 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Jan 2024 10:44:35.4476 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JKCadZBL/1UFzH288m7+JkqdwQTXRoPPCzWBVpbYU5YacIH3RJ+FFH00M2DrAii39/B45rvKnwFMDu4sRT/Jzw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8332 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: icBsVfbUp2F4zf9OjyPQ0YFtx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=wfFetMBR; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=none; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") [AMD Official Use Only - General] Ok, I got it! Thanks. Abner > -----Original Message----- > From: Xing, Eric > Sent: Tuesday, January 23, 2024 6:28 PM > To: Chang, Abner ; Attar, AbdulLateef (Abdul > Lateef) ; devel@edk2.groups.io; Zhai, MingXin > (Duke) > Cc: Fu, Igniculus > Subject: RE: [edk2-devel] [PATCH 29/33] AMD/VanGoghBoard: Check in > SmramSaveState module. > > [AMD Official Use Only - General] > > Hi Abner and Abdul, > Thanks for the review, it is good catch. > Currently, our current override files are based on UDK202208 code base no= w. > AmdMmSaveStateLib.inf is not existed in UDK2208 code base, we will > leverage latest EDK2 changes after we update to new EDK2 code base. > > Thanks, > Eric > > > -----Original Message----- > > From: Chang, Abner > > Sent: Tuesday, January 23, 2024 1:16 PM > > To: Attar, AbdulLateef (Abdul Lateef) ; > > devel@edk2.groups.io; Zhai, MingXin (Duke) > > Cc: Xing, Eric ; Fu, Igniculus > > Subject: RE: [edk2-devel] [PATCH 29/33] AMD/VanGoghBoard: Check in > > SmramSaveState module. > > > > [AMD Official Use Only - General] > > > > Yeah, please check if AMD specific SaveStatelib library under > > UefiCpuPkg/Library/MmSaveStateLib can cover the change or not. > > > > Thanks > > Abner > > > > > -----Original Message----- > > > From: Attar, AbdulLateef (Abdul Lateef) > > > Sent: Saturday, January 20, 2024 10:38 PM > > > To: devel@edk2.groups.io; Zhai, MingXin (Duke) > > > Cc: Xing, Eric ; Fu, Igniculus > > > ; Chang, Abner > > > Subject: RE: [edk2-devel] [PATCH 29/33] AMD/VanGoghBoard: Check in > > > SmramSaveState module. > > > > > > [AMD Official Use Only - General] > > > > > > Why overriding the PiSmmCpuDxeSmm driver? > > > UefiCpuPkg has AMD specific SaveStatelib library > > > "UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf". > > > > > > Thanks > > > AbduL > > > > > > -----Original Message----- > > > From: devel@edk2.groups.io On Behalf Of > > > duke.zhai via groups.io > > > Sent: Thursday, January 18, 2024 12:21 PM > > > To: devel@edk2.groups.io > > > Cc: Xing, Eric ; Zhai, MingXin (Duke) > > > ; Fu, Igniculus ; Chang, > > > Abner > > > Subject: [edk2-devel] [PATCH 29/33] AMD/VanGoghBoard: Check in > > > SmramSaveState module. > > > > > > Caution: This message originated from an External Source. Use proper > > > caution when opening attachments, clicking links, or responding. > > > > > > > > > From: Duke Zhai > > > > > > > > > BZ #:4640 > > > > > > Initial SmramSaveState module. > > > > > > This module provides services to access SMRAM Save State Map. > > > > > > > > > > > > Signed-off-by: Ken Yao > > > > > > Cc: Eric Xing > > > > > > Cc: Duke Zhai > > > > > > Cc: Igniculus Fu > > > > > > Cc: Abner Chang > > > > > > --- > > > > > > .../PiSmmCpuDxeSmm/SmramSaveState.c | 715 > > > ++++++++++++++++++ > > > > > > 1 file changed, 715 insertions(+) > > > > > > create mode 100644 > > > > > Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeS > > m > > > m/SmramSaveState.c > > > > > > > > > > > > diff --git > > > > > > a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxe > > > Smm/SmramSaveState.c > > > > > > b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxe > > > Smm/SmramSaveState.c > > > > > > new file mode 100644 > > > > > > index 0000000000..9e5a7d59fc > > > > > > --- /dev/null > > > > > > +++ > > > > > > b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxe > > > Smm/SmramSaveState.c > > > > > > @@ -0,0 +1,715 @@ > > > > > > +/** @file > > > > > > + Implements SmramSaveState.c > > > > > > + > > > > > > + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights > > > + reserved.
> > > > > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > + > > > > > > +**/ > > > > > > + > > > > > > +/* This file includes code originally published under the following > > > +license. */ > > > > > > + > > > > > > +/** @file > > > > > > +Provides services to access SMRAM Save State Map > > > > > > + > > > > > > +Copyright (c) 2010 - 2019, Intel Corporation. All rights > > > +reserved.
> > > > > > +SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > + > > > > > > +**/ > > > > > > + > > > > > > +#include > > > > > > + > > > > > > +#include > > > > > > + > > > > > > +#include > > > > > > +#include > > > > > > +#include > > > > > > +#include > > > > > > + > > > > > > +#include "PiSmmCpuDxeSmm.h" > > > > > > + > > > > > > +typedef struct { > > > > > > + UINT64 Signature; // Offse= t 0x00 > > > > > > + UINT16 Reserved1; // Offse= t 0x08 > > > > > > + UINT16 Reserved2; // Offse= t 0x0A > > > > > > + UINT16 Reserved3; // Offse= t 0x0C > > > > > > + UINT16 SmmCs; // Offse= t 0x0E > > > > > > + UINT16 SmmDs; // Offse= t 0x10 > > > > > > + UINT16 SmmSs; // Offse= t 0x12 > > > > > > + UINT16 SmmOtherSegment; // Offse= t 0x14 > > > > > > + UINT16 Reserved4; // Offse= t 0x16 > > > > > > + UINT64 Reserved5; // Offse= t 0x18 > > > > > > + UINT64 Reserved6; // Offse= t 0x20 > > > > > > + UINT64 Reserved7; // Offse= t 0x28 > > > > > > + UINT64 SmmGdtPtr; // Offse= t 0x30 > > > > > > + UINT32 SmmGdtSize; // Offse= t 0x38 > > > > > > + UINT32 Reserved8; // Offse= t 0x3C > > > > > > + UINT64 Reserved9; // Offse= t 0x40 > > > > > > + UINT64 Reserved10; // Offse= t 0x48 > > > > > > + UINT16 Reserved11; // Offse= t 0x50 > > > > > > + UINT16 Reserved12; // Offse= t 0x52 > > > > > > + UINT32 Reserved13; // Offse= t 0x54 > > > > > > + UINT64 Reserved14; // Offse= t 0x58 > > > > > > +} PROCESSOR_SMM_DESCRIPTOR; > > > > > > + > > > > > > +extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd; > > > > > > + > > > > > > +// > > > > > > +// EFER register LMA bit > > > > > > +// > > > > > > +#define LMA BIT10 > > > > > > + > > > > > > +/// > > > > > > +/// Macro used to simplify the lookup table entries of type > > > CPU_SMM_SAVE_STATE_LOOKUP_ENTRY > > > > > > +/// > > > > > > +#define SMM_CPU_OFFSET(Field) OFFSET_OF > > (SMRAM_SAVE_STATE_MAP, > > > Field) > > > > > > + > > > > > > +/// > > > > > > +/// Macro used to simplify the lookup table entries of type > > > CPU_SMM_SAVE_STATE_REGISTER_RANGE > > > > > > +/// > > > > > > +#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + = 1 > > > +} > > > > > > + > > > > > > +/// > > > > > > +/// Structure used to describe a range of registers > > > > > > +/// > > > > > > +typedef struct { > > > > > > + EFI_SMM_SAVE_STATE_REGISTER Start; > > > > > > + EFI_SMM_SAVE_STATE_REGISTER End; > > > > > > + UINTN Length; > > > > > > +} CPU_SMM_SAVE_STATE_REGISTER_RANGE; > > > > > > + > > > > > > +/// > > > > > > +/// Structure used to build a lookup table to retrieve the widths an= d > > > +offsets > > > > > > +/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER > > value > > > > > > +/// > > > > > > + > > > > > > +#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1 > > > > > > +#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2 > > > > > > +#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3 > > > > > > +#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 4 > > > > > > + > > > > > > +typedef struct { > > > > > > + UINT8 Width32; > > > > > > + UINT8 Width64; > > > > > > + UINT16 Offset32; > > > > > > + UINT16 Offset64Lo; > > > > > > + UINT16 Offset64Hi; > > > > > > + BOOLEAN Writeable; > > > > > > +} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY; > > > > > > + > > > > > > +/// > > > > > > +/// Structure used to build a lookup table for the IOMisc width > > > +information > > > > > > +/// > > > > > > +typedef struct { > > > > > > + UINT8 Width; > > > > > > + EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth; > > > > > > +} CPU_SMM_SAVE_STATE_IO_WIDTH; > > > > > > + > > > > > > +/// > > > > > > +/// Variables from SMI Handler > > > > > > +/// > > > > > > +X86_ASSEMBLY_PATCH_LABEL gPatchSmbase; > > > > > > +X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack; > > > > > > +X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3; > > > > > > +extern volatile UINT8 gcSmiHandlerTemplate[]; > > > > > > +extern CONST UINT16 gcSmiHandlerSize; > > > > > > + > > > > > > +// > > > > > > +// Variables used by SMI Handler > > > > > > +// > > > > > > +IA32_DESCRIPTOR gSmiHandlerIdtr; > > > > > > + > > > > > > +/// > > > > > > +/// Table used by GetRegisterIndex() to convert an > > > EFI_SMM_SAVE_STATE_REGISTER > > > > > > +/// value to an index into a table of type > > > CPU_SMM_SAVE_STATE_LOOKUP_ENTRY > > > > > > +/// > > > > > > +CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE > > > mSmmCpuRegisterRanges[] =3D { > > > > > > + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, > > > EFI_SMM_SAVE_STATE_REGISTER_LDTINFO), > > > > > > + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, > > > EFI_SMM_SAVE_STATE_REGISTER_RIP), > > > > > > + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, > > > EFI_SMM_SAVE_STATE_REGISTER_CR4), > > > > > > + { (EFI_SMM_SAVE_STATE_REGISTER)0, > > > (EFI_SMM_SAVE_STATE_REGISTER)0, 0} > > > > > > +}; > > > > > > + > > > > > > +/// > > > > > > +/// Lookup table used to retrieve the widths and offsets associated > > > +with each > > > > > > +/// supported EFI_SMM_SAVE_STATE_REGISTER value > > > > > > +/// > > > > > > +CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY > mSmmCpuWidthOffset[] > > =3D > > > { > > > > > > + { 0, 0, 0, 0, = 0, > > FALSE }, // > > > Reserved > > > > > > + > > > > > > + // > > > > > > + // CPU Save State registers defined in PI SMM CPU Protocol. > > > > > > + // > > > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64.GdtrBase= LoDword), > > > SMM_CPU_OFFSET (x64.GdtrBaseHiDword), FALSE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_GDTBASE =3D 4 > > > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64.IdtrBase= LoDword), > > > SMM_CPU_OFFSET (x64.IdtrBaseHiDword), FALSE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_IDTBASE =3D 5 > > > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64.LdtrBase= LoDword), > > > SMM_CPU_OFFSET (x64.LdtrBaseHiDword), FALSE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_LDTBASE =3D 6 > > > > > > + { 0, 0, 0, SMM_CPU_OFFSET (x64.GdtrLimi= t), 0, > > > FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT =3D 7 > > > > > > + { 0, 0, 0, SMM_CPU_OFFSET (x64.IdtrLimi= t), 0, > > > FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT =3D 8 > > > > > > + { 0, 0, 0, SMM_CPU_OFFSET (x64.LdtrLimi= t), 0, > > > FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT =3D 9 > > > > > > + { 0, 0, 0, 0, = 0, > > FALSE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_LDTINFO =3D 10 > > > > > > + > > > > > > + { 4, 4, SMM_CPU_OFFSET (x86._ES), SMM_CPU_OFFSET (x64._ES), > > > 0, FALSE }, // EFI_SMM_SAVE_STATE= _REGISTER_ES > > =3D 20 > > > > > > + { 4, 4, SMM_CPU_OFFSET (x86._CS), SMM_CPU_OFFSET (x64._CS), > > > 0, FALSE }, // EFI_SMM_SAVE_STATE= _REGISTER_CS > > =3D 21 > > > > > > + { 4, 4, SMM_CPU_OFFSET (x86._SS), SMM_CPU_OFFSET (x64._SS), > > > 0, FALSE }, // EFI_SMM_SAVE_STATE= _REGISTER_SS > > =3D 22 > > > > > > + { 4, 4, SMM_CPU_OFFSET (x86._DS), SMM_CPU_OFFSET (x64._DS), > > > 0, FALSE }, // EFI_SMM_SAVE_STATE= _REGISTER_DS > > =3D 23 > > > > > > + { 4, 4, SMM_CPU_OFFSET (x86._FS), SMM_CPU_OFFSET (x64._FS), > > > 0, FALSE }, // EFI_SMM_SAVE_STATE= _REGISTER_FS > > =3D 24 > > > > > > + { 4, 4, SMM_CPU_OFFSET (x86._GS), SMM_CPU_OFFSET (x64._GS), > > > 0, FALSE }, // EFI_SMM_SAVE_STATE= _REGISTER_GS > > =3D 25 > > > > > > + { 0, 4, 0, SMM_CPU_OFFSET (x64.LdtrSele= ctor), 0, > > > FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL =3D 26 > > > > > > + { 4, 4, SMM_CPU_OFFSET (x86._TR), SMM_CPU_OFFSET > > (x64.TrSelector), > > > 0, FALSE }, // > > EFI_SMM_SAVE_STATE_REGISTER_TR_SEL =3D > > > 27 > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._DR7), SMM_CPU_OFFSET (x64._DR7), > > > SMM_CPU_OFFSET (x64._DR7) + 4, FALSE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_DR7 =3D 28 > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._DR6), SMM_CPU_OFFSET (x64._DR6), > > > SMM_CPU_OFFSET (x64._DR6) + 4, FALSE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_DR6 =3D 29 > > > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R8), > > > SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_R8 =3D 30 > > > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R9), > > > SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_R9 =3D 31 > > > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R10), > > > SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_R10 =3D 32 > > > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R11), > > > SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_R11 =3D 33 > > > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R12), > > > SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_R12 =3D 34 > > > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R13), > > > SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_R13 =3D 35 > > > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R14), > > > SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_R14 =3D 36 > > > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R15), > > > SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_R15 =3D 37 > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EAX), SMM_CPU_OFFSET (x64._RAX), > > > SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_RAX =3D 38 > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EBX), SMM_CPU_OFFSET (x64._RBX), > > > SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_RBX =3D 39 > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._ECX), SMM_CPU_OFFSET (x64._RCX), > > > SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_RCX =3D 40 > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EDX), SMM_CPU_OFFSET (x64._RDX), > > > SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_RDX =3D 41 > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._ESP), SMM_CPU_OFFSET (x64._RSP), > > > SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_RSP =3D 42 > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EBP), SMM_CPU_OFFSET (x64._RBP), > > > SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_RBP =3D 43 > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._ESI), SMM_CPU_OFFSET (x64._RSI), > > > SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_RSI =3D 44 > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EDI), SMM_CPU_OFFSET (x64._RDI), > > > SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_RDI =3D 45 > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EIP), SMM_CPU_OFFSET (x64._RIP), > > > SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_RIP =3D 46 > > > > > > + > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS), SMM_CPU_OFFSET > > > (x64._RFLAGS), SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE },= // > > > EFI_SMM_SAVE_STATE_REGISTER_RFLAGS =3D 51 > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._CR0), SMM_CPU_OFFSET (x64._CR0), > > > SMM_CPU_OFFSET (x64._CR0) + 4, FALSE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_CR0 =3D 52 > > > > > > + { 4, 8, SMM_CPU_OFFSET (x86._CR3), SMM_CPU_OFFSET (x64._CR3), > > > SMM_CPU_OFFSET (x64._CR3) + 4, FALSE }, // > > > EFI_SMM_SAVE_STATE_REGISTER_CR3 =3D 53 > > > > > > + { 0, 4, 0, SMM_CPU_OFFSET (x64._CR4), = 0, > > > FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 =3D 54 > > > > > > +}; > > > > > > + > > > > > > +/// > > > > > > +/// Lookup table for the IOMisc width information > > > > > > +/// > > > > > > +CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] =3D { > > > > > > + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = =3D 0 > > > > > > + { 1, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // > > > SMM_IO_LENGTH_BYTE =3D 1 > > > > > > + { 2, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 }, // > > > SMM_IO_LENGTH_WORD =3D 2 > > > > > > + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = =3D 3 > > > > > > + { 4, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 }, // > > > SMM_IO_LENGTH_DWORD =3D 4 > > > > > > + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = =3D 5 > > > > > > + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = =3D 6 > > > > > > + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 } // Undefined = =3D 7 > > > > > > +}; > > > > > > + > > > > > > +/// > > > > > > +/// Lookup table for the IOMisc type information > > > > > > +/// > > > > > > +CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] =3D { > > > > > > + EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_DX > > > =3D 0 > > > > > > + EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_IN_DX > > =3D 1 > > > > > > + EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_OUTS > > =3D > > > 2 > > > > > > + EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_INS > > =3D 3 > > > > > > + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = =3D 4 > > > > > > + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = =3D 5 > > > > > > + EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // > > SMM_IO_TYPE_REP_OUTS > > > =3D 6 > > > > > > + EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // > > SMM_IO_TYPE_REP_INS > > > =3D 7 > > > > > > + EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // > > > SMM_IO_TYPE_OUT_IMMEDIATE =3D 8 > > > > > > + EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // > > > SMM_IO_TYPE_OUT_IMMEDIATE =3D 9 > > > > > > + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = =3D 10 > > > > > > + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = =3D 11 > > > > > > + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = =3D 12 > > > > > > + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = =3D 13 > > > > > > + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = =3D 14 > > > > > > + (EFI_SMM_SAVE_STATE_IO_TYPE)0 // Undefined = =3D 15 > > > > > > +}; > > > > > > + > > > > > > +/// > > > > > > +/// The mode of the CPU at the time an SMI occurs > > > > > > +/// > > > > > > +UINT8 mSmmSaveStateRegisterLma; > > > > > > + > > > > > > +/** > > > > > > + Read information from the CPU save state. > > > > > > + > > > > > > + @param Register Specifies the CPU register to read form the save > > state. > > > > > > + > > > > > > + @retval 0 Register is not valid > > > > > > + @retval >0 Index into mSmmCpuWidthOffset[] associated with > > > + Register > > > > > > + > > > > > > +**/ > > > > > > +UINTN > > > > > > +GetRegisterIndex ( > > > > > > + IN EFI_SMM_SAVE_STATE_REGISTER Register > > > > > > + ) > > > > > > +{ > > > > > > + UINTN Index; > > > > > > + UINTN Offset; > > > > > > + > > > > > > + for (Index =3D 0, Offset =3D SMM_SAVE_STATE_REGISTER_MAX_INDEX; > > > mSmmCpuRegisterRanges[Index].Length !=3D 0; Index++) { > > > > > > + if ((Register >=3D mSmmCpuRegisterRanges[Index].Start) && (Regis= ter > > > + <=3D > > > mSmmCpuRegisterRanges[Index].End)) { > > > > > > + return Register - mSmmCpuRegisterRanges[Index].Start + Offset; > > > > > > + } > > > > > > + > > > > > > + Offset +=3D mSmmCpuRegisterRanges[Index].Length; > > > > > > + } > > > > > > + > > > > > > + return 0; > > > > > > +} > > > > > > + > > > > > > +/** > > > > > > + Read a CPU Save State register on the target processor. > > > > > > + > > > > > > + This function abstracts the differences that whether the CPU Save > > > + State > > > register is in the > > > > > > + IA32 CPU Save State Map or X64 CPU Save State Map. > > > > > > + > > > > > > + This function supports reading a CPU Save State register in SMBase > > > relocation handler. > > > > > > + > > > > > > + @param[in] CpuIndex Specifies the zero-based index of the C= PU > > save > > > state. > > > > > > + @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up > > > table. > > > > > > + @param[in] Width The number of bytes to read from the CP= U > > save > > > state. > > > > > > + @param[out] Buffer Upon return, this holds the CPU registe= r value > > read > > > from the save state. > > > > > > + > > > > > > + @retval EFI_SUCCESS The register was read from Save Stat= e. > > > > > > + @retval EFI_NOT_FOUND The register is not defined for the = Save > > State > > > of Processor. > > > > > > + @retval EFI_INVALID_PARAMETER This or Buffer is NULL. > > > > > > + > > > > > > +**/ > > > > > > +EFI_STATUS > > > > > > +ReadSaveStateRegisterByIndex ( > > > > > > + IN UINTN CpuIndex, > > > > > > + IN UINTN RegisterIndex, > > > > > > + IN UINTN Width, > > > > > > + OUT VOID *Buffer > > > > > > + ) > > > > > > +{ > > > > > > + SMRAM_SAVE_STATE_MAP *CpuSaveState; > > > > > > + > > > > > > + if (RegisterIndex =3D=3D 0) { > > > > > > + return EFI_NOT_FOUND; > > > > > > + } > > > > > > + > > > > > > + CpuSaveState =3D gSmst->CpuSaveState[CpuIndex]; > > > > > > + > > > > > > + if (mSmmSaveStateRegisterLma =3D=3D > > > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { > > > > > > + // > > > > > > + // If 32-bit mode width is zero, then the specified register can > > > + not be > > > accessed > > > > > > + // > > > > > > + if (mSmmCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { > > > > > > + return EFI_NOT_FOUND; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // If Width is bigger than the 32-bit mode width, then the > > > + specified register > > > can not be accessed > > > > > > + // > > > > > > + if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) { > > > > > > + return EFI_INVALID_PARAMETER; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // Write return buffer > > > > > > + // > > > > > > + ASSERT (CpuSaveState !=3D NULL); > > > > > > + CopyMem (Buffer, (UINT8 *)CpuSaveState + > > > mSmmCpuWidthOffset[RegisterIndex].Offset32, Width); > > > > > > + } else { > > > > > > + // > > > > > > + // If 64-bit mode width is zero, then the specified register can > > > + not be > > > accessed > > > > > > + // > > > > > > + if (mSmmCpuWidthOffset[RegisterIndex].Width64 =3D=3D 0) { > > > > > > + return EFI_NOT_FOUND; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // If Width is bigger than the 64-bit mode width, then the > > > + specified register > > > can not be accessed > > > > > > + // > > > > > > + if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) { > > > > > > + return EFI_INVALID_PARAMETER; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // Write at most 4 of the lower bytes of the return buffer > > > > > > + // > > > > > > + CopyMem (Buffer, (UINT8 *)CpuSaveState + > > > mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN (4, Width)); > > > > > > + if (Width > 4) { > > > > > > + // > > > > > > + // Write at most 4 of the upper bytes of the return buffer > > > > > > + // > > > > > > + CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + > > > mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4); > > > > > > + } > > > > > > + } > > > > > > + > > > > > > + return EFI_SUCCESS; > > > > > > +} > > > > > > + > > > > > > +/** > > > > > > + Read a CPU Save State register on the target processor. > > > > > > + > > > > > > + This function abstracts the differences that whether the CPU Save > > > + State > > > register is in the > > > > > > + IA32 CPU Save State Map or X64 CPU Save State Map. > > > > > > + > > > > > > + This function supports reading a CPU Save State register in SMBase > > > relocation handler. > > > > > > + > > > > > > + @param[in] CpuIndex Specifies the zero-based index of the C= PU > > save > > > state. > > > > > > + @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up > > > table. > > > > > > + @param[in] Width The number of bytes to read from the CP= U > > save > > > state. > > > > > > + @param[out] Buffer Upon return, this holds the CPU registe= r value > > read > > > from the save state. > > > > > > + > > > > > > + @retval EFI_SUCCESS The register was read from Save Stat= e. > > > > > > + @retval EFI_NOT_FOUND The register is not defined for the = Save > > State > > > of Processor. > > > > > > + @retval EFI_INVALID_PARAMETER Buffer is NULL, or Width does not > > > + meet > > > requirement per Register type. > > > > > > + > > > > > > +**/ > > > > > > +EFI_STATUS > > > > > > +EFIAPI > > > > > > +ReadSaveStateRegister ( > > > > > > + IN UINTN CpuIndex, > > > > > > + IN EFI_SMM_SAVE_STATE_REGISTER Register, > > > > > > + IN UINTN Width, > > > > > > + OUT VOID *Buffer > > > > > > + ) > > > > > > +{ > > > > > > + SMRAM_SAVE_STATE_MAP *CpuSaveState; > > > > > > + EFI_SMM_SAVE_STATE_IO_INFO *IoInfo; > > > > > > + > > > > > > + CpuSaveState =3D gSmst->CpuSaveState[CpuIndex]; > > > > > > + // > > > > > > + // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA > > > > > > + // > > > > > > + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA) { > > > > > > + // > > > > > > + // Only byte access is supported for this register > > > > > > + // > > > > > > + if (Width !=3D 1) { > > > > > > + return EFI_INVALID_PARAMETER; > > > > > > + } > > > > > > + > > > > > > + *(UINT8 *)Buffer =3D mSmmSaveStateRegisterLma; > > > > > > + > > > > > > + return EFI_SUCCESS; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO > > > > > > + // > > > > > > + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_IO) { > > > > > > + // > > > > > > + // Check SMM IO Trap Offset valid bit > > > > > > + // > > > > > > + if (!(CpuSaveState->x64.SMM_IO_TRAP & 0x02)) { > > > > > > + return EFI_NOT_FOUND; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // Zero the IoInfo structure that will be returned in Buffer > > > > > > + // > > > > > > + IoInfo =3D (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer; > > > > > > + ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO)); > > > > > > + > > > > > > + // > > > > > > + // Use hard code to fill in all the fields of the IoInfo > > > + structure > > > > > > + // > > > > > > + IoInfo->IoPort =3D (UINT16)(CpuSaveState->x64.SMM_IO_TRAP >> 16= ); > > > > > > + IoInfo->IoWidth =3D EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8; > > > > > > + IoInfo->IoType =3D EFI_SMM_SAVE_STATE_IO_TYPE_INPUT; > > > > > > + IoInfo->IoData =3D (UINT64)IoRead8 ((CpuSaveState- > >x64.SMM_IO_TRAP > > > >> 16)); > > > > > > + > > > > > > + return EFI_SUCCESS; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // Convert Register to a register lookup table index > > > > > > + // > > > > > > + return ReadSaveStateRegisterByIndex (CpuIndex, GetRegisterIndex > > > (Register), Width, Buffer); > > > > > > +} > > > > > > + > > > > > > +/** > > > > > > + Write value to a CPU Save State register on the target processor. > > > > > > + > > > > > > + This function abstracts the differences that whether the CPU Save > > > + State > > > register is in the > > > > > > + IA32 CPU Save State Map or X64 CPU Save State Map. > > > > > > + > > > > > > + This function supports writing a CPU Save State register in SMBase > > > relocation handler. > > > > > > + > > > > > > + @param[in] CpuIndex Specifies the zero-based index of the CP= U > > save > > > state. > > > > > > + @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up > > > table. > > > > > > + @param[in] Width The number of bytes to read from the CPU > > save > > > state. > > > > > > + @param[in] Buffer Upon entry, this holds the new CPU regis= ter > > value. > > > > > > + > > > > > > + @retval EFI_SUCCESS The register was written to Save Sta= te. > > > > > > + @retval EFI_NOT_FOUND The register is not defined for the = Save > > State > > > of Processor. > > > > > > + @retval EFI_INVALID_PARAMETER ProcessorIndex or Width is not > > correct. > > > > > > + > > > > > > +**/ > > > > > > +EFI_STATUS > > > > > > +EFIAPI > > > > > > +WriteSaveStateRegister ( > > > > > > + IN UINTN CpuIndex, > > > > > > + IN EFI_SMM_SAVE_STATE_REGISTER Register, > > > > > > + IN UINTN Width, > > > > > > + IN CONST VOID *Buffer > > > > > > + ) > > > > > > +{ > > > > > > + UINTN RegisterIndex; > > > > > > + SMRAM_SAVE_STATE_MAP *CpuSaveState; > > > > > > + > > > > > > + // > > > > > > + // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored > > > > > > + // > > > > > > + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA) { > > > > > > + return EFI_SUCCESS; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported > > > > > > + // > > > > > > + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_IO) { > > > > > > + return EFI_NOT_FOUND; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // Convert Register to a register lookup table index > > > > > > + // > > > > > > + RegisterIndex =3D GetRegisterIndex (Register); > > > > > > + if (RegisterIndex =3D=3D 0) { > > > > > > + return EFI_NOT_FOUND; > > > > > > + } > > > > > > + > > > > > > + CpuSaveState =3D gSmst->CpuSaveState[CpuIndex]; > > > > > > + > > > > > > + // > > > > > > + // Do not write non-writable SaveState, because it will cause exce= ption. > > > > > > + // > > > > > > + if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) { > > > > > > + return EFI_UNSUPPORTED; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // Check CPU mode > > > > > > + // > > > > > > + if (mSmmSaveStateRegisterLma =3D=3D > > > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { > > > > > > + // > > > > > > + // If 32-bit mode width is zero, then the specified register can > > > + not be > > > accessed > > > > > > + // > > > > > > + if (mSmmCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { > > > > > > + return EFI_NOT_FOUND; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // If Width is bigger than the 32-bit mode width, then the > > > + specified register > > > can not be accessed > > > > > > + // > > > > > > + if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) { > > > > > > + return EFI_INVALID_PARAMETER; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // Write SMM State register > > > > > > + // > > > > > > + ASSERT (CpuSaveState !=3D NULL); > > > > > > + CopyMem ((UINT8 *)CpuSaveState + > > > mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width); > > > > > > + } else { > > > > > > + // > > > > > > + // If 64-bit mode width is zero, then the specified register can > > > + not be > > > accessed > > > > > > + // > > > > > > + if (mSmmCpuWidthOffset[RegisterIndex].Width64 =3D=3D 0) { > > > > > > + return EFI_NOT_FOUND; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // If Width is bigger than the 64-bit mode width, then the > > > + specified register > > > can not be accessed > > > > > > + // > > > > > > + if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) { > > > > > > + return EFI_INVALID_PARAMETER; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // Write at most 4 of the lower bytes of SMM State register > > > > > > + // > > > > > > + CopyMem ((UINT8 *)CpuSaveState + > > > mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, > Width)); > > > > > > + if (Width > 4) { > > > > > > + // > > > > > > + // Write at most 4 of the upper bytes of SMM State register > > > > > > + // > > > > > > + CopyMem ((UINT8 *)CpuSaveState + > > > mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, > > > Width > > > - 4); > > > > > > + } > > > > > > + } > > > > > > + > > > > > > + return EFI_SUCCESS; > > > > > > +} > > > > > > + > > > > > > +/** > > > > > > + Hook the code executed immediately after an RSM instruction on the > > > currently > > > > > > + executing CPU. The mode of code executed immediately after RSM > > > + must be > > > > > > + detected, and the appropriate hook must be selected. Always clear > > > + the auto > > > > > > + HALT restart flag if it is set. > > > > > > + > > > > > > + @param[in] CpuIndex The processor index for the cu= rrently > > > > > > + executing CPU. > > > > > > + @param[in] CpuState Pointer to SMRAM Save State Ma= p for > > the > > > > > > + currently executing CPU. > > > > > > + @param[in] NewInstructionPointer32 Instruction pointer to use if > > > resuming to > > > > > > + 32-bit mode from 64-bit SMM. > > > > > > + @param[in] NewInstructionPointer Instruction pointer to use if > > resuming > > > to > > > > > > + same mode as SMM. > > > > > > + > > > > > > + @retval The value of the original instruction pointer before it wa= s > > hooked. > > > > > > + > > > > > > +**/ > > > > > > +UINT64 > > > > > > +EFIAPI > > > > > > +HookReturnFromSmm ( > > > > > > + IN UINTN CpuIndex, > > > > > > + SMRAM_SAVE_STATE_MAP *CpuState, > > > > > > + UINT64 NewInstructionPointer32, > > > > > > + UINT64 NewInstructionPointer > > > > > > + ) > > > > > > +{ > > > > > > + UINT64 OriginalInstructionPointer; > > > > > > + > > > > > > + OriginalInstructionPointer =3D SmmCpuFeaturesHookReturnFromSmm ( > > > > > > + CpuIndex, > > > > > > + CpuState, > > > > > > + NewInstructionPointer32, > > > > > > + NewInstructionPointer > > > > > > + ); > > > > > > + if (OriginalInstructionPointer !=3D 0) { > > > > > > + return OriginalInstructionPointer; > > > > > > + } > > > > > > + > > > > > > + if (mSmmSaveStateRegisterLma =3D=3D > > > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { > > > > > > + OriginalInstructionPointer =3D (UINT64)CpuState->x86._EIP; > > > > > > + CpuState->x86._EIP =3D (UINT32)NewInstructionPointer; > > > > > > + // > > > > > > + // Clear the auto HALT restart flag so the RSM instruction > > > + returns > > > > > > + // program control to the instruction following the HLT instruct= ion. > > > > > > + // > > > > > > + if ((CpuState->x86.AutoHALTRestart & BIT0) !=3D 0) { > > > > > > + CpuState->x86.AutoHALTRestart &=3D ~BIT0; > > > > > > + } > > > > > > + } else { > > > > > > + OriginalInstructionPointer =3D CpuState->x64._RIP; > > > > > > + if ((CpuState->x64.EFER & LMA) =3D=3D 0) { > > > > > > + CpuState->x64._RIP =3D (UINT32)NewInstructionPointer32; > > > > > > + } else { > > > > > > + CpuState->x64._RIP =3D (UINT32)NewInstructionPointer; > > > > > > + } > > > > > > + > > > > > > + // > > > > > > + // Clear the auto HALT restart flag so the RSM instruction > > > + returns > > > > > > + // program control to the instruction following the HLT instruct= ion. > > > > > > + // > > > > > > + if ((CpuState->x64.AutoHALTRestart & BIT0) !=3D 0) { > > > > > > + CpuState->x64.AutoHALTRestart &=3D ~BIT0; > > > > > > + } > > > > > > + } > > > > > > + > > > > > > + return OriginalInstructionPointer; > > > > > > +} > > > > > > + > > > > > > +/** > > > > > > + Get the size of the SMI Handler in bytes. > > > > > > + > > > > > > + @retval The size, in bytes, of the SMI Handler. > > > > > > + > > > > > > +**/ > > > > > > +UINTN > > > > > > +EFIAPI > > > > > > +GetSmiHandlerSize ( > > > > > > + VOID > > > > > > + ) > > > > > > +{ > > > > > > + UINTN Size; > > > > > > + > > > > > > + Size =3D SmmCpuFeaturesGetSmiHandlerSize (); > > > > > > + if (Size !=3D 0) { > > > > > > + return Size; > > > > > > + } > > > > > > + > > > > > > + return gcSmiHandlerSize; > > > > > > +} > > > > > > + > > > > > > +/** > > > > > > + Install the SMI handler for the CPU specified by CpuIndex. This > > > + function > > > > > > + is called by the CPU that was elected as monarch during System > > > Management > > > > > > + Mode initialization. > > > > > > + > > > > > > + @param[in] CpuIndex The index of the CPU to install the custom S= MI > > > handler. > > > > > > + The value must be between 0 and the > > > + NumberOfCpus field > > > > > > + in the System Management System Table (SMST)= . > > > > > > + @param[in] SmBase The SMBASE address for the CPU specified by > > > CpuIndex. > > > > > > + @param[in] SmiStack The stack to use when an SMI is processed by > > the > > > > > > + the CPU specified by CpuIndex. > > > > > > + @param[in] StackSize The size, in bytes, if the stack used when a= n > > > + SMI is > > > > > > + processed by the CPU specified by CpuIndex. > > > > > > + @param[in] GdtBase The base address of the GDT to use when an > > SMI is > > > > > > + processed by the CPU specified by CpuIndex. > > > > > > + @param[in] GdtSize The size, in bytes, of the GDT used when an = SMI > > is > > > > > > + processed by the CPU specified by CpuIndex. > > > > > > + @param[in] IdtBase The base address of the IDT to use when an S= MI > > is > > > > > > + processed by the CPU specified by CpuIndex. > > > > > > + @param[in] IdtSize The size, in bytes, of the IDT used when an = SMI is > > > > > > + processed by the CPU specified by CpuIndex. > > > > > > + @param[in] Cr3 The base address of the page tables to use w= hen > > an SMI > > > > > > + is processed by the CPU specified by CpuInde= x. > > > > > > +**/ > > > > > > +VOID > > > > > > +EFIAPI > > > > > > +InstallSmiHandler ( > > > > > > + IN UINTN CpuIndex, > > > > > > + IN UINT32 SmBase, > > > > > > + IN VOID *SmiStack, > > > > > > + IN UINTN StackSize, > > > > > > + IN UINTN GdtBase, > > > > > > + IN UINTN GdtSize, > > > > > > + IN UINTN IdtBase, > > > > > > + IN UINTN IdtSize, > > > > > > + IN UINT32 Cr3 > > > > > > + ) > > > > > > +{ > > > > > > + PROCESSOR_SMM_DESCRIPTOR *Psd; > > > > > > + UINT32 CpuSmiStack; > > > > > > + > > > > > > + // > > > > > > + // Initialize PROCESSOR_SMM_DESCRIPTOR > > > > > > + // > > > > > > + Psd =3D (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + > > > SMM_PSD_OFFSET); > > > > > > + CopyMem (Psd, &gcPsd, sizeof (gcPsd)); > > > > > > + Psd->SmmGdtPtr =3D (UINT64)GdtBase; > > > > > > + Psd->SmmGdtSize =3D (UINT32)GdtSize; > > > > > > + > > > > > > + if (SmmCpuFeaturesGetSmiHandlerSize () !=3D 0) { > > > > > > + // > > > > > > + // Install SMI handler provided by library > > > > > > + // > > > > > > + SmmCpuFeaturesInstallSmiHandler ( > > > > > > + CpuIndex, > > > > > > + SmBase, > > > > > > + SmiStack, > > > > > > + StackSize, > > > > > > + GdtBase, > > > > > > + GdtSize, > > > > > > + IdtBase, > > > > > > + IdtSize, > > > > > > + Cr3 > > > > > > + ); > > > > > > + return; > > > > > > + } > > > > > > + > > > > > > + InitShadowStack (CpuIndex, (VOID *)((UINTN)SmiStack + StackSize)); > > > > > > + > > > > > > + // > > > > > > + // Initialize values in template before copy > > > > > > + // > > > > > > + CpuSmiStack =3D (UINT32)((UINTN)SmiStack + StackSize - sizeof > > > + (UINTN)); > > > > > > + PatchInstructionX86 (gPatchSmiStack, CpuSmiStack, 4); > > > > > > + PatchInstructionX86 (gPatchSmiCr3, Cr3, 4); > > > > > > + PatchInstructionX86 (gPatchSmbase, SmBase, 4); > > > > > > + gSmiHandlerIdtr.Base =3D IdtBase; > > > > > > + gSmiHandlerIdtr.Limit =3D (UINT16)(IdtSize - 1); > > > > > > + > > > > > > + // > > > > > > + // Set the value at the top of the CPU stack to the CPU Index > > > > > > + // > > > > > > + *(UINTN *)(UINTN)CpuSmiStack =3D CpuIndex; > > > > > > + > > > > > > + // > > > > > > + // Copy template to CPU specific SMI handler location > > > > > > + // > > > > > > + CopyMem ( > > > > > > + (VOID *)((UINTN)SmBase + SMM_HANDLER_OFFSET), > > > > > > + (VOID *)gcSmiHandlerTemplate, > > > > > > + gcSmiHandlerSize > > > > > > + ); > > > > > > +} > > > > > > -- > > > > > > 2.31.1 > > > > > > > > > > > > > > > > > >=20 > > > > > > > > > -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114192): https://edk2.groups.io/g/devel/message/114192 Mute This Topic: https://groups.io/mt/103831200/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-