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Reviewed-by: Jiaxin Wu > -----Original Message----- > From: Tan, Dun > Sent: Friday, May 17, 2024 5:45 PM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Kumar, Rahul R ; > Gerd Hoffmann ; Wu, Jiaxin ; > Zhou, Jianfeng > Subject: [PATCH] UefiCpuPkg:fix issue when splitting paging entry >=20 > This patch is to fix issue when splitting leaf paging > entry in CpuPageTableLib code. >=20 > In previous code, before we assign the new child paging > structure address to the content of splitted paging entry, > PageTableLibSetPnle() is called to make sure the bit7 is > set to 0, which indicate the previous leaf entry is > changed to non-leaf entry now. There is a gap between > we change the bit7 and we assign the new child paging > structure address to the content of the splitted paging > entry. If the address of code execution or data access > happens to be in the range covered by the splitted paging > entry, this gap may cause issue. >=20 > In this patch, we prepare the new paging entry content > value in a local variable and assign the value to the > splitted paging entry at once. The volatile keyword > is used to ensure that no optimization will occur in > compilation. >=20 > Signed-off-by: Dun Tan > Cc: Ray Ni > Cc: Rahul Kumar > Cc: Gerd Hoffmann > Cc: Jiaxin Wu > Cc: Zhou Jianfeng > --- > UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > index b10a3008e4..bdc411338f 100644 > --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > @@ -342,6 +342,7 @@ PageTableLibMapInLevel ( > UINT64 PhysicalAddrInAttr; > IA32_PAGING_ENTRY OriginalParentPagingEntry; > IA32_PAGING_ENTRY OriginalCurrentPagingEntry; > + IA32_PAGING_ENTRY TempPagingEntry; >=20 > ASSERT (Level !=3D 0); > ASSERT ((Attribute !=3D NULL) && (Mask !=3D NULL)); > @@ -359,6 +360,8 @@ PageTableLibMapInLevel ( >=20 > OriginalParentPagingEntry.Uint64 =3D ParentPagingEntry->Uint64; > OneOfPagingEntry.Uint64 =3D 0; > + TempPagingEntry.Uint64 =3D 0; > + > // > // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 <<= 21) > or 4K (1 << 12). > // > @@ -441,8 +444,10 @@ PageTableLibMapInLevel ( > // Non-leaf entry doesn't have PAT bit. So use > ~IA32_PE_BASE_ADDRESS_MASK_40 is to make sure PAT bit > // (bit12) in original big-leaf entry is not assigned to PageTable= BaseAddress > field of non-leaf entry. > // > - PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, > &AllOneMask); > - ParentPagingEntry->Uint64 =3D ((UINTN)(VOID *)PagingEntry) | > (ParentPagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40)); > + TempPagingEntry.Uint64 =3D ParentPagingEntry->Uint64; > + PageTableLibSetPnle (&TempPagingEntry.Pnle, &NopAttribute, > &AllOneMask); > + TempPagingEntry.Uint64 =3D ((UINTN)(VOID= *)PagingEntry) | > (TempPagingEntry.Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40)); > + *(volatile UINT64 *)&(ParentPagingEntry->Uint64) =3D > TempPagingEntry.Uint64; > } > } else { > // > -- > 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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