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cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.22; Thu, 25 Apr 2024 01:54:37 +0000 X-Received: from MN0PR11MB6158.namprd11.prod.outlook.com ([fe80::b0c8:dcaf:59ea:9e99]) by MN0PR11MB6158.namprd11.prod.outlook.com ([fe80::b0c8:dcaf:59ea:9e99%6]) with mapi id 15.20.7519.021; Thu, 25 Apr 2024 01:54:37 +0000 From: "Wu, Jiaxin" To: "devel@edk2.groups.io" , "kraxel@redhat.com" CC: Ard Biesheuvel , "Yao, Jiewen" , "Ni, Ray" Subject: Re: [edk2-devel] [PATCH v3 08/13] OvmfPkg/PlatformInitLib: Create gEfiSmmSmramMemoryGuid Thread-Topic: [edk2-devel] [PATCH v3 08/13] OvmfPkg/PlatformInitLib: Create gEfiSmmSmramMemoryGuid Thread-Index: AQHalWA1zBvqODpvrE2R+k29oKYKFLF1xUuwgAGXsICAAM+6EA== Date: Thu, 25 Apr 2024 01:54:37 +0000 Message-ID: References: <20240418065556.5696-1-jiaxin.wu@intel.com> <20240418065556.5696-9-jiaxin.wu@intel.com> <74uoxthjxoztfpmnt552eysn2u2blko6tkllnk3a76ax46yf5d@y34m4b4h6t57> In-Reply-To: <74uoxthjxoztfpmnt552eysn2u2blko6tkllnk3a76ax46yf5d@y34m4b4h6t57> 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List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 24 Apr 2024 18:54:41 -0700 Resent-From: jiaxin.wu@intel.com Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Atg04gpKqambpIAGs8qPKnm1x7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=r7J99lIX; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io >=20 > SmramInternal.c handles that. It creates two regions, one is a page at > the start of SMRAM where S3 state is stored (and marked as allocated), > one is all the rest. >=20 Yes, the same logic is moved to the OvmfPkg/Library/PlatformInitLib/MemDete= ct.c: // // Create first SMRAM descriptor, which contains data structures used i= n S3 resume. // One page is enough for the data structure // SmramHobDescriptorBlock->Descriptor[0].PhysicalStart =3D PlatformInfoHo= b->LowMemory - TsegSize; SmramHobDescriptorBlock->Descriptor[0].CpuStart =3D PlatformInfoHo= b->LowMemory - TsegSize; SmramHobDescriptorBlock->Descriptor[0].PhysicalSize =3D EFI_PAGE_SIZE; SmramHobDescriptorBlock->Descriptor[0].RegionState =3D EFI_SMRAM_CLOS= ED | EFI_CACHEABLE | EFI_ALLOCATED; // // Create second SMRAM descriptor, which is free and will be used by SM= M foundation. // SmramHobDescriptorBlock->Descriptor[1].PhysicalStart =3D SmramHobDescri= ptorBlock->Descriptor[0].PhysicalStart + EFI_PAGE_SIZE; SmramHobDescriptorBlock->Descriptor[1].CpuStart =3D SmramHobDescri= ptorBlock->Descriptor[0].CpuStart + EFI_PAGE_SIZE; SmramHobDescriptorBlock->Descriptor[1].PhysicalSize =3D TsegSize - EFI= _PAGE_SIZE; SmramHobDescriptorBlock->Descriptor[1].RegionState =3D EFI_SMRAM_CLOS= ED | EFI_CACHEABLE; > So, if you need some smram to initialize SMM in PEI I'd suggest to > either add a third region, or make the first region larger. >=20 > It's not clear to me why you put the logic upside down and introduce > that HOB in the first place. >=20 Let me explain more why need this change: 1. The EFI_SMM_SMRAM_MEMORY_GUID HOB, as defined in the PI specification, i= s used to describe the SMRAM memory regions supported by the platform. This= HOB should be produced during the memory detection phase to align with the= PI spec. 2. In addition to the memory reserved for ACPI S3 resume, an increasing num= ber of features require reserving SMRAM for specific purposes, such as SmmR= elocation. Other advanced features in Intel platforms also necessitate this= . The implementation of these features varies and is entirely dependent on = the platform. This is why an increasing number of platforms are adopting th= e EFI_SMM_SMRAM_MEMORY_GUID HOB for SMRAM description. 3. It is crucial that the SMRAM information remains consistent when retriev= ed from the platform, whether through the SMM ACCESS PPI/Protocol or the EF= I_SMM_SMRAM_MEMORY_GUID HOB. Inconsistencies can lead to unexpected issues,= most commonly memory region conflicts. 4. The SMM ACCESS PPI/Protocol can be naturally implemented for general use= . The common approach is to utilize the EFI_SMM_SMRAM_MEMORY_GUID HOB. For = reference, see the existing implementation in the EDK2 repository at edk2/U= efiPayloadPkg/SmmAccessDxe/SmmAccessDxe.inf and edk2-platforms/Silicon/Inte= l/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib= .inf.=20 For the reasons mentioned, we are moving the SMRAM memory regions to HOBs a= nd allowing SMM access to consume these HOBs. I will add the above info into commit message. >=20 > Storing anything SMM related outside SMRAM makes me nervous. > I'd strongly suggest to avoid that. >=20 > It might be that in this specific case it is not a problem. But it > needs very careful review of the implications (which I have not done) > and you have to hope you don't miss a possible attack vector, such as > someone modifying the HOB and the firmware then storing SMM data + code > outside SMRAM. >=20 Understand, but here is the case we can record the info in non-smram since = PI spec exposes that, there is no difference the info retrieved from PPI/ n= on-smm Protocol or the non-smram. Thanks, Jiaxin -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#118253): https://edk2.groups.io/g/devel/message/118253 Mute This Topic: https://groups.io/mt/105593577/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-