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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks Gerd, I will add more info to explain the reversed mem info. but I d= on't want add the size info because it depends on the producer. Just indica= te it should cover what contents for each cpu. > -----Original Message----- > From: Gerd Hoffmann > Sent: Tuesday, February 14, 2023 6:20 PM > To: Wu, Jiaxin > Cc: devel@edk2.groups.io; Dong, Eric ; Ni, Ray > ; Zeng, Star ; Laszlo Ersek > ; Kumar, Rahul R > Subject: Re: [PATCH v7 3/6] UefiCpuPkg/SmmBaseHob.h: Add SMM Base > HOB Data >=20 > On Tue, Feb 14, 2023 at 04:33:11PM +0800, Jiaxin Wu wrote: > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4337 > > > > The default SMBASE for the x86 processor is 0x30000. When > > SMI happens, CPU runs the SMI handler at SMBASE+0x8000. > > Also, the SMM save state area is within SMBASE+0x10000. > > > > One of the SMM initialization from CPU perspective is to relocate > > and program the new SMBASE (in TSEG range) for each CPU thread. When > > the SMBASE relocation happens in a PEI module, the PEI module shall > > produce the SMM_BASE_HOB in HOB database which tells the > > PiSmmCpuDxeSmm driver (runs at a later phase) about the new SMBASE > > for each CPU thread. PiSmmCpuDxeSmm driver installs the SMI handler > > at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Index. > When > > the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and > > program the new SMBASE itself. > > > > This patch adds the SMM Base HOB for any PEI module to do > > the SmBase relocation ahead of PiSmmCpuDxeSmm driver and > > store the relocated SmBase address in array for reach > > Processors. > > > > Cc: Eric Dong > > Cc: Ray Ni > > Cc: Zeng Star > > Cc: Laszlo Ersek > > Cc: Gerd Hoffmann > > Cc: Rahul Kumar > > Signed-off-by: Jiaxin Wu > > --- > > UefiCpuPkg/Include/Guid/SmmBaseHob.h | 64 > ++++++++++++++++++++++++++++++++++++ > > UefiCpuPkg/UefiCpuPkg.dec | 5 ++- > > 2 files changed, 68 insertions(+), 1 deletion(-) > > create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h > > > > diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h > b/UefiCpuPkg/Include/Guid/SmmBaseHob.h > > new file mode 100644 > > index 0000000000..4aae0d23ff > > --- /dev/null > > +++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h > > @@ -0,0 +1,64 @@ > > +/** @file > > + The Smm Base HOB is used to store the information of: > > + * The relocated SmBase address in array for each Processors. > > + > > + The default SMBASE for the x86 processor is 0x30000. When SMI > happens, CPU > > + runs the SMI handler at SMBASE+0x8000. Also, the SMM save state area > is within > > + SMBASE+0x10000. > > + > > + One of the SMM initialization from CPU perspective is to relocate an= d > program > > + the new SMBASE (in TSEG range) for each CPU thread. When the > SMBASE relocation > > + happens in a PEI module, the PEI module shall produce the > SMM_BASE_HOB in HOB > > + database which tells the PiSmmCpuDxeSmm driver (which runs at a late= r > phase) > > + about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm driver > installs the > > + SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU > thread Index. > > + When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate > and program > > + the new SMBASE itself. >=20 > This should also explain the consequences of the tiling allocation, i.e. > each cpu has one page at SMBASE+0x8000 for the SMI handler and one page > at SMBASE+0xF000 for the CPU state. >=20 > take care, > Gerd