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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Gerd, >=20 > Ok, so TileSize is what the firmware needs to store code and state. > Where does the SIZE_8KB come from? I assume this is the amount of > per-cpu memory allocated by the PEI module? Shouldn't this be passed > in the HOB instead of being hard-coded? >=20 Yes, TileSize is for firmware store code and data, including 3 parts: 1. CPU SMRAM Save State Map starts at SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET(= 0xfc00), 2. extra CPU specific context start starts at SMBASE + SMM_PSD_OFFSET (PROC= ESSOR SMM DESCRIPTO, 0xfb00), 3. SMI entry point starts at SMBASE + SMM_HANDLER_OFFSET (0x8000). This size is rounded up to nearest power of 2. So, you can refer the below = existing algorithm: TileCodeSize =3D GetSmiHandlerSize (); TileCodeSize =3D ALIGN_VALUE (TileCodeSize, SIZE_4KB); TileDataSize =3D (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof = (SMRAM_SAVE_STATE_MAP); TileDataSize =3D ALIGN_VALUE (TileDataSize, SIZE_4KB); TileSize =3D TileDataSize + TileCodeSize - 1; TileSize =3D 2 * GetPowerOfTwo32 ((UINT32)TileSize); DEBUG ((DEBUG_INFO, "SMRAM TileSize =3D 0x%08x (0x%08x, 0x%08x)\n", TileS= ize, TileCodeSize, TileDataSize)); Based on above, we hardcode the size to 8k, because It's almost impossible = to exceed 8k for total code & data size. So, there is the hard requirement = that SMI Entry Size <=3D 0x1000, data Size < 0x1000 in pi smm cpu driver. T= o simplify the usage, we add the size check as below to catch this very lit= tle possibility case instead of passing or defining the new interface for t= hat, which means we add such rigorous processed assumption to avoid define = the new interface that may not be changed and used.=20 In PEI module, it also has such assumption, so we don't pass in the HOB for= the resolved smbase mem size, because we have avoided the possibility of e= rror in the reference pi smm cpu driver. if (TileSize > SIZE_8KB) { DEBUG ((DEBUG_ERROR, "The Range of Smbase in SMRAM is not enough -- R= equired TileSize =3D 0x%08x, Actual TileSize =3D 0x%08x\n", TileSize, SIZE_= 8KB)); CpuDeadLoop (); return RETURN_BUFFER_TOO_SMALL; } > > + // Allocate buffer for all of the tiles. > > + // > > + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual > > + // Volume 3C, Section 34.11 SMBASE Relocation > > + // For Pentium and Intel486 processors, the SMBASE values must b= e > > + // aligned on a 32-KByte boundary or the processor will enter > shutdown > > + // state during the execution of a RSM instruction. > > + // > > + // Intel486 processors: FamilyId is 4 > > + // Pentium processors : FamilyId is 5 > > + // > > + BufferPages =3D EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * > (mMaxNumberOfCpus - 1)); >=20 > I think correct is: > BufferPages =3D EFI_SIZE_TO_PAGES(TileSize * mMaxNumberOfCpus); >=20 This is the existing code logic & it's correct, not wrong, I don't change i= t. To understand that, we need understand the algorithm of smbase: The SIZE_32KB covers the *several* SMI Entry and Save State of CPU 0, while= TileSize * (mMaxNumberOfCpus - 1) to cover Save State of CPU 1+, not inclu= de the cpu0, so, it's the mMaxNumberOfCpus - 1.=20 > > + if ((FamilyId =3D=3D 4) || (FamilyId =3D=3D 5)) { > > + Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_32KB); >=20 > Does that actually matter still? I'm pretty sure we can safely use > "ASSERT(FamilyId > 5)" here. Pentium processors have been built in > the last century, predating x64. >=20 This is the existing code logic. I don't change it. If you think we don't n= eed it, please file Bugzilla for change. > Beside that the code is broken for SMP, only cpu0 will get a properly > aligned smbase. Not sure penium processors support SMP in the first > place though ... >=20 I don't understand why "only cpu0 will get a properly aligned smbase" > > for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { > > - mCpuHotPlugData.SmBase[Index] =3D (UINTN)Buffer + Index = * > TileSize - SMM_HANDLER_OFFSET; > > + mCpuHotPlugData.SmBase[Index] =3D mSmmRelocated ? > (UINTN)SmmBaseHobData->SmBase[Index] : (UINTN)Buffer + Index * > TileSize - SMM_HANDLER_OFFSET; >=20 > For Index =3D 0 this evaluates to "Buffer - SMM_HANDLER_OFFSET", which > looks > wrong to me. >=20 No, it's correct, we don't allocate the buffer for [smbase 0, smbase + smi = handler), we just record the address of smbase 0, there is no need for the = [smbase 0, smbase + smi handler) usage. Thanks, Jiaxin