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charset="us-ascii" Content-Transfer-Encoding: quoted-printable I will write a test code and update the results in next patch series. Regarding the buffer data port read. Reading the spec I am not entirely su= re on the behavior of the host when the data transfer is not aligned to DWO= RD boundary. I will test it with width set to 32bit and if that works I wil= l fix it in v2. Thanks, Mateusz > -----Original Message----- > From: Wu, Hao A > Sent: Wednesday, February 5, 2020 4:16 AM > To: devel@edk2.groups.io; Albecki, Mateusz > Cc: Marcin Wojtas ; Gao, Zhichao > ; Gao, Liming > Subject: RE: [edk2-devel] [PATCH 4/4] MdeModulePkg/SdMmcPciHcDxe: Fix > PIO transfer mode >=20 > > -----Original Message----- > > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > > Albecki, Mateusz > > Sent: Monday, February 03, 2020 10:19 PM > > To: devel@edk2.groups.io > > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas; Gao, Zhichao; Gao, > > Liming > > Subject: [edk2-devel] [PATCH 4/4] MdeModulePkg/SdMmcPciHcDxe: Fix > PIO > > transfer mode > > > > Current driver does not support PIO transfer mode for commands other > > then tuning. This change adds the code to transfer PIO data. >=20 >=20 > Hello Mateusz, >=20 > Try to provide some feedbacks before I can test the patch. >=20 > One test request, is it possible for you to test the asynchronous transf= er for > the PIO mode? >=20 > A possible method can be using an UEFI application to locate the BlockIO= 2 > protocol from a specific SD or eMMC device (which forced to PIO transfer > mode). > And test with the WriteBlocksEx() & ReadBlocksEx() services to see if th= e RW > is successful. >=20 > Also, one more inline comment below: >=20 >=20 > > > > Cc: Hao A Wu > > Cc: Marcin Wojtas > > Cc: Zhichao Gao > > Cc: Liming Gao > > > > Signed-off-by: Mateusz Albecki > > --- > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 3 + > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 113 > > +++++++++++++++++---- > > 2 files changed, 95 insertions(+), 21 deletions(-) > > > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > > index 15b7d12596..fd89306fab 100644 > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > > @@ -157,6 +157,9 @@ typedef struct { > > UINT64 Timeout; > > UINT32 Retries; > > > > + BOOLEAN PioModeTransferCompleted; > > + UINT32 PioBlockIndex; > > + > > SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc; > > SD_MMC_HC_ADMA_64_V3_DESC_LINE *Adma64V3Desc; > > SD_MMC_HC_ADMA_64_V4_DESC_LINE *Adma64V4Desc; > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > index 480a1664ea..43703974f7 100644 > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > @@ -1711,6 +1711,8 @@ SdMmcPrintTrb ( > > DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb- > > >CommandComplete)); > > DEBUG ((DebugLevel, "Timeout: %d\n", Trb->Timeout)); > > DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries)); > > + DEBUG ((DebugLevel, "PioModeTransferCompleted: %d\n", Trb- > > >PioModeTransferCompleted)); > > + DEBUG ((DebugLevel, "PioBlockIndex: %d\n", Trb->PioBlockIndex)); > > DEBUG ((DebugLevel, "Adma32Desc: %X\n", Trb->Adma32Desc)); > > DEBUG ((DebugLevel, "Adma64V3Desc: %X\n", Trb->Adma64V3Desc)); > > DEBUG ((DebugLevel, "Adma64V4Desc: %X\n", Trb->Adma64V4Desc)); > > @@ -1762,6 +1764,8 @@ SdMmcCreateTrb ( > > Trb->CommandComplete =3D FALSE; > > Trb->Timeout =3D Packet->Timeout; > > Trb->Retries =3D SD_MMC_TRB_RETRIES; > > + Trb->PioModeTransferCompleted =3D FALSE; > > + Trb->PioBlockIndex =3D 0; > > Trb->Private =3D Private; > > > > if ((Packet->InTransferLength !=3D 0) && (Packet->InDataBuffer !=3D= NULL)) { > > @@ -2447,6 +2451,85 @@ SdMmcCheckCommandComplete ( > > return EFI_NOT_READY; > > } > > > > +/** > > + Transfers data from card using PIO method. > > + > > + @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA > > instance. > > + @param[in] Trb The pointer to the SD_MMC_HC_TRB instance. > > + @param[in] IntStatus Snapshot of the normal interrupt status regis= ter. > > + > > + @retval EFI_SUCCESS PIO transfer completed successfully. > > + @retval EFI_NOT_READY PIO transfer completion still pending. > > + @retval Others PIO transfer failed to complete. > > +**/ > > +EFI_STATUS > > +SdMmcTransferDataWithPio ( > > + IN SD_MMC_HC_PRIVATE_DATA *Private, > > + IN SD_MMC_HC_TRB *Trb, > > + IN UINT16 IntStatus > > + ) > > +{ > > + EFI_STATUS Status; > > + UINT16 Data16; > > + UINT32 BlockCount; > > + > > + BlockCount =3D (Trb->DataLen / Trb->BlockSize); > > + if (Trb->DataLen % Trb->BlockSize !=3D 0) { > > + BlockCount +=3D 1; > > + } > > + > > + if (Trb->PioBlockIndex >=3D BlockCount) { > > + return EFI_SUCCESS; > > + } > > + > > + if (Trb->Read) { > > + if ((IntStatus & BIT5) =3D=3D 0) { > > + return EFI_NOT_READY; > > + } > > + Data16 =3D BIT5; > > + SdMmcHcRwMmio (Private->PciIo, Trb->Slot, > > SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data16), &Data16); > > + > > + Status =3D Private->PciIo->Mem.Read ( > > + Private->PciIo, > > + EfiPciIoWidthFifoUint8, > > + Trb->Slot, > > + SD_MMC_HC_BUF_DAT_PORT, > > + Trb->BlockSize, > > + (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * Trb- > > >PioBlockIndex)) > > + ); >=20 >=20 > The read (write) process will be: >=20 > 1. Wait for the Buffer Read (Write) Ready to set; > 2. Clear the Buffer Read (Write) Ready bit; > 3. Access the Buffer Data Port register 'Trb->BlockSize' times, each tim= e > consuming 1 byte to get all the data in a block. >=20 > Since we are accessing the Buffer Data Port register, same BAR offset, s= o > 'EfiPciIoWidthFifoUint8' is used here. >=20 > Is my understanding correct? >=20 > If so, I am thinking is it less efficient during the read/write of the d= ata? > Since the Buffer Data Port register is 4-byte in width, data can be acce= ssed > at most 4 bytes a time. Not sure if doing so can save time for the PIO t= ransfer. >=20 > Best Regards, > Hao Wu >=20 >=20 > > + if (EFI_ERROR (Status)) { > > + return Status; > > + } > > + Trb->PioBlockIndex++; > > + } else { > > + if ((IntStatus & BIT4) =3D=3D 0) { > > + return EFI_NOT_READY; > > + } > > + Data16 =3D BIT4; > > + SdMmcHcRwMmio (Private->PciIo, Trb->Slot, > > SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data16), &Data16); > > + > > + Status =3D Private->PciIo->Mem.Write ( > > + Private->PciIo, > > + EfiPciIoWidthFifoUint8, > > + Trb->Slot, > > + SD_MMC_HC_BUF_DAT_PORT, > > + Trb->BlockSize, > > + (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * Trb- > > >PioBlockIndex)) > > + ); > > + if (EFI_ERROR (Status)) { > > + return Status; > > + } > > + Trb->PioBlockIndex++; > > + } > > + > > + if (Trb->PioBlockIndex >=3D BlockCount) { > > + Trb->PioModeTransferCompleted =3D TRUE; > > + return EFI_SUCCESS; > > + } else { > > + return EFI_NOT_READY; > > + } > > +} > > + > > /** > > Update the SDMA address on the SDMA buffer boundary interrupt. > > > > @@ -2531,6 +2614,13 @@ SdMmcCheckDataTransfer ( > > return Status; > > } > > > > + if (Trb->Mode =3D=3D SdMmcPioMode && !Trb- > >PioModeTransferCompleted) { > > + Status =3D SdMmcTransferDataWithPio (Private, Trb, IntStatus); > > + if (EFI_ERROR (Status)) { > > + return Status; > > + } > > + } > > + > > if ((Trb->Mode =3D=3D SdMmcSdmaMode) && ((IntStatus & BIT3) !=3D 0)= ) { > > Data16 =3D BIT3; > > Status =3D SdMmcHcRwMmio ( > > @@ -2573,7 +2663,6 @@ SdMmcCheckTrbResult ( > > EFI_STATUS Status; > > EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; > > UINT16 IntStatus; > > - UINT32 PioLength; > > > > Packet =3D Trb->Packet; > > // > > @@ -2609,26 +2698,8 @@ SdMmcCheckTrbResult ( > > (Packet->SdMmcCmdBlk->CommandIndex =3D=3D > > EMMC_SEND_TUNING_BLOCK)) || > > ((Private->Slot[Trb->Slot].CardType =3D=3D SdCardType) && > > (Packet->SdMmcCmdBlk->CommandIndex =3D=3D > > SD_SEND_TUNING_BLOCK))) { > > - // > > - // When performing tuning procedure (Execute Tuning is set to 1) > through > > PIO mode, > > - // wait Buffer Read Ready bit of Normal Interrupt Status Register= to be 1. > > - // Refer to SD Host Controller Simplified Specification 3.0 figur= e 2-29 for > > details. > > - // > > - if ((IntStatus & BIT5) =3D=3D BIT5) { > > - // > > - // Clear Buffer Read Ready interrupt at first. > > - // > > - IntStatus =3D BIT5; > > - SdMmcHcRwMmio (Private->PciIo, Trb->Slot, > > SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus); > > - // > > - // Read data out from Buffer Port register > > - // > > - for (PioLength =3D 0; PioLength < Trb->DataLen; PioLength +=3D = 4) { > > - SdMmcHcRwMmio (Private->PciIo, Trb->Slot, > > SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength); > > - } > > - Status =3D EFI_SUCCESS; > > - goto Done; > > - } > > + Status =3D SdMmcTransferDataWithPio (Private, Trb, IntStatus); > > + goto Done; > > } > > > > if (!Trb->CommandComplete) { > > -- > > 2.14.1.windows.1 > > > > -------------------------------------------------------------------- > > > > Intel Technology Poland sp. z o.o. > > ul. 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