* [PATCH 0/1] MdeModulePkg/SdMmcPciHcDxe: Increase driver reliability
@ 2020-02-21 15:17 Albecki, Mateusz
2020-02-21 15:17 ` [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency Albecki, Mateusz
0 siblings, 1 reply; 4+ messages in thread
From: Albecki, Mateusz @ 2020-02-21 15:17 UTC (permalink / raw)
To: devel; +Cc: Mateusz Albecki, Hao A Wu, Marcin Wojtas, Zhichao Gao, Liming Gao
This patch series aims to increase the reliability of the eMMC detection by
exectuing the SEND_STATUS after SWITCH command on the lower frequency. Currently
the driver will first switch the frequency to the new target and then execute
SEND_STATUS to see if SWITCH was a success. While this behavior is not against the
eMMC/SD specification it has been observed that on some designs switching to
HS200 @200MHz will make the SEND_STATUS fail consitently with CRC error(5/5 times) while if
we skip the SEND_STATUS and execute the clock tuning the link remains stable. My working
theory (unconfirmed) is that CMD lane Tx path works fine so host is able to send command to the device
(and that is why the clock tuning passes) but Rx path is broken so when device transmits
response the CRC error is signaled(tuning command is a special case that doesn't send
response on CMD). After the tuning is executed the CMD line seems to be working properly.
Tests:
- Several platforms that have been failing before(some of them with 100% repro rate) have been stress tested and are able to detect eMMC device every time
Spec compliance:
While the spec doesn't require or forbids the host from sending the SEND_STATUS at any point in cards operation
(with the exception of busy polling the SWITCH change but we are not doing that anyway) the HS200 switch
sequence in eMMC 5.1 specification section 6.6.2.2 indicates that host may send SEND_STATUS before changing the
frequency. While it is not a hard requierment some eMMC vendors have indicated that the driver is at fault for
not following the spec. After this patch the SEND_STATUS of every frequency upgrade path, including the switch
from legacy timing -> HS200, will be sent before the frequency increase which will bring the driver closer to
spec(although I don't think it can be said the driver violated it in the first place).
Github
https://github.com/malbecki/edk2/tree/emmc_stable_send_status
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Marcin Wojtas <mw@semihalf.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Mateusz Albecki (1):
MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 124 +++++++++++++++++----
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 2 +-
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 1 +
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 2 +
4 files changed, 105 insertions(+), 24 deletions(-)
--
2.14.1.windows.1
--------------------------------------------------------------------
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency
2020-02-21 15:17 [PATCH 0/1] MdeModulePkg/SdMmcPciHcDxe: Increase driver reliability Albecki, Mateusz
@ 2020-02-21 15:17 ` Albecki, Mateusz
2020-02-24 7:00 ` Wu, Hao A
0 siblings, 1 reply; 4+ messages in thread
From: Albecki, Mateusz @ 2020-02-21 15:17 UTC (permalink / raw)
To: devel; +Cc: Mateusz Albecki, Hao A Wu, Marcin Wojtas, Zhichao Gao, Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140
To avoid stability issues on some designs the driver
will now send SEND_STATUS at previous, lower, frequency
when upgrading the bus timing.
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Marcin Wojtas <mw@semihalf.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com>
---
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 124 +++++++++++++++++----
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 2 +-
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 1 +
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 2 +
4 files changed, 105 insertions(+), 24 deletions(-)
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index 776c0e796c..c2ebd37623 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -558,6 +558,41 @@ EmmcTuningClkForHs200 (
return EFI_DEVICE_ERROR;
}
+/**
+ Check the SWITCH operation status.
+
+ @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The SWITCH finished siccessfully.
+ @retval others The SWITCH failed.
+**/
+EFI_STATUS
+EmmcCheckSwitchStatus (
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca
+ )
+{
+ EFI_STATUS Status;
+ UINT32 DevStatus;
+
+ Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: Send status fails with %r\n", Status));
+ return Status;
+ }
+
+ //
+ // Check the switch operation is really successful or not.
+ //
+ if ((DevStatus & BIT7) != 0) {
+ DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: The switch operation fails as DevStatus is 0x%08x\n", DevStatus));
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
/**
Switch the bus width to specified width.
@@ -591,7 +626,6 @@ EmmcSwitchBusWidth (
UINT8 Index;
UINT8 Value;
UINT8 CmdSet;
- UINT32 DevStatus;
//
// Write Byte, the Value field is written into the byte pointed by Index.
@@ -617,24 +651,53 @@ EmmcSwitchBusWidth (
return Status;
}
- Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
+ Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Send status fails with %r\n", Status));
return Status;
}
- //
- // Check the switch operation is really successful or not.
- //
- if ((DevStatus & BIT7) != 0) {
- DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: The switch operation fails as DevStatus is 0x%08x\n", DevStatus));
- return EFI_DEVICE_ERROR;
- }
Status = SdMmcHcSetBusWidth (PciIo, Slot, BusWidth);
return Status;
}
+/**
+ Checks if given clock frequency is supported on
+ given bus timing.
+
+ @param[in] ClockFreq Clock frequency to check in KHz.
+ @param[in] BusTiming Bus timing against which frequency will be compared.
+
+ @retval TRUE Frequency is valid for given bus timing.
+ @retval FALSE Frequency is invalid for given bus timing.
+**/
+BOOLEAN
+EmmcIsFrequencySupportedOnBusTiming (
+ IN UINT64 ClockFreq,
+ IN SD_MMC_BUS_MODE BusTiming
+ )
+{
+ UINT32 MaxFreq;
+
+ switch (BusTiming) {
+ case SdMmcMmcLegacy:
+ MaxFreq = 26000;
+ break;
+ case SdMmcMmcHsSdr:
+ case SdMmcMmcHsDdr:
+ MaxFreq = 52000;
+ break;
+ case SdMmcMmcHs200:
+ case SdMmcMmcHs400:
+ MaxFreq = 200000;
+ break;
+ default:
+ return FALSE;
+ }
+
+ return (ClockFreq <= MaxFreq);
+}
+
/**
Switch the bus timing and clock frequency.
@@ -669,9 +732,9 @@ EmmcSwitchBusTiming (
UINT8 Index;
UINT8 Value;
UINT8 CmdSet;
- UINT32 DevStatus;
SD_MMC_HC_PRIVATE_DATA *Private;
UINT8 HostCtrl1;
+ BOOLEAN DelaySendStatus;
Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
//
@@ -695,7 +758,7 @@ EmmcSwitchBusTiming (
Value = 0;
break;
default:
- DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported BusTiming(%d\n)", BusTiming));
+ DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported BusTiming(%d)\n", BusTiming));
return EFI_INVALID_PARAMETER;
}
@@ -724,6 +787,27 @@ EmmcSwitchBusTiming (
return Status;
}
+ //
+ // For cases when we switch bus timing to higher mode from current we want to
+ // send SEND_STATUS at current, lower, frequency then the target frequency to avoid
+ // stability issues. It has been observed that some designs are unable to process the
+ // SEND_STATUS at higher frequency during switch to HS200 @200MHz irrespective of the number of retries
+ // and only running the clock tuning is able to make them work on target frequency.
+ //
+ // For cases when we are downgrading the frequency and current high frequency is invalid
+ // we have to first change the frequency to target frequency and then send the SEND_STATUS.
+ //
+ if (EmmcIsFrequencySupportedOnBusTiming (Private->Slot[Slot].CurrentFreq, BusTiming) &&
+ (Private->Slot[Slot].CurrentFreq < (ClockFreq * 1000))) {
+ Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ DelaySendStatus = FALSE;
+ } else {
+ DelaySendStatus = TRUE;
+ }
+
//
// Convert the clock freq unit from MHz to KHz.
//
@@ -732,17 +816,11 @@ EmmcSwitchBusTiming (
return Status;
}
- Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Send status fails with %r\n", Status));
- return Status;
- }
- //
- // Check the switch operation is really successful or not.
- //
- if ((DevStatus & BIT7) != 0) {
- DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: The switch operation fails as DevStatus is 0x%08x\n", DevStatus));
- return EFI_DEVICE_ERROR;
+ if (DelaySendStatus) {
+ Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
}
return Status;
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
index b18ff3e972..57f4cf329a 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
@@ -28,7 +28,7 @@ EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding = {
NULL
};
-#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, \
+#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, 0, \
{EDKII_SD_MMC_BUS_WIDTH_IGNORE,\
EDKII_SD_MMC_CLOCK_FREQ_IGNORE,\
{EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE}}}
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
index 5bc3577ba2..bb3d38482f 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
@@ -83,6 +83,7 @@ typedef struct {
BOOLEAN MediaPresent;
BOOLEAN Initialized;
SD_MMC_CARD_TYPE CardType;
+ UINT64 CurrentFreq;
EDKII_SD_MMC_OPERATING_PARAMETERS OperatingParameters;
} SD_MMC_HC_SLOT;
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 43626fff48..7971196a25 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -931,6 +931,8 @@ SdMmcHcClockSupply (
}
}
+ Private->Slot[Slot].CurrentFreq = ClockFreq;
+
return Status;
}
--
2.14.1.windows.1
--------------------------------------------------------------------
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek
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This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by
others is strictly prohibited.
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency
2020-02-21 15:17 ` [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency Albecki, Mateusz
@ 2020-02-24 7:00 ` Wu, Hao A
2020-02-24 10:10 ` Albecki, Mateusz
0 siblings, 1 reply; 4+ messages in thread
From: Wu, Hao A @ 2020-02-24 7:00 UTC (permalink / raw)
To: Albecki, Mateusz, devel@edk2.groups.io
Cc: Marcin Wojtas, Gao, Zhichao, Gao, Liming
> -----Original Message-----
> From: Albecki, Mateusz
> Sent: Friday, February 21, 2020 11:17 PM
> To: devel@edk2.groups.io
> Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas; Gao, Zhichao; Gao, Liming
> Subject: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS
> at lower frequency
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140
>
> To avoid stability issues on some designs the driver
> will now send SEND_STATUS at previous, lower, frequency
> when upgrading the bus timing.
Hello Mateusz,
The patch looks like a refinement. So I plan to push it (after the reviewing
process) after the upcoming stable tag. Does it work for you?
A couple of inline comments below:
>
> Cc: Hao A Wu <hao.a.wu@intel.com>
> Cc: Marcin Wojtas <mw@semihalf.com>
> Cc: Zhichao Gao <zhichao.gao@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
>
> Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com>
> ---
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 124
> +++++++++++++++++----
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 2 +-
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 1 +
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 2 +
> 4 files changed, 105 insertions(+), 24 deletions(-)
>
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> index 776c0e796c..c2ebd37623 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> @@ -558,6 +558,41 @@ EmmcTuningClkForHs200 (
> return EFI_DEVICE_ERROR;
> }
>
> +/**
> + Check the SWITCH operation status.
> +
> + @param[in] PassThru A pointer to the
> EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
Please help to add the comments for parameters 'Slot' and 'Rca'.
> +
> + @retval EFI_SUCCESS The SWITCH finished siccessfully.
> + @retval others The SWITCH failed.
> +**/
> +EFI_STATUS
> +EmmcCheckSwitchStatus (
> + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
> + IN UINT8 Slot,
> + IN UINT16 Rca
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 DevStatus;
> +
> + Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: Send status fails
> with %r\n", Status));
> + return Status;
> + }
> +
> + //
> + // Check the switch operation is really successful or not.
> + //
> + if ((DevStatus & BIT7) != 0) {
> + DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: The switch
> operation fails as DevStatus is 0x%08x\n", DevStatus));
> + return EFI_DEVICE_ERROR;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> /**
> Switch the bus width to specified width.
>
> @@ -591,7 +626,6 @@ EmmcSwitchBusWidth (
> UINT8 Index;
> UINT8 Value;
> UINT8 CmdSet;
> - UINT32 DevStatus;
>
> //
> // Write Byte, the Value field is written into the byte pointed by Index.
> @@ -617,24 +651,53 @@ EmmcSwitchBusWidth (
> return Status;
> }
>
> - Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
> + Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);
> if (EFI_ERROR (Status)) {
> - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Send status fails
> with %r\n", Status));
> return Status;
> }
> - //
> - // Check the switch operation is really successful or not.
> - //
> - if ((DevStatus & BIT7) != 0) {
> - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: The switch operation
> fails as DevStatus is 0x%08x\n", DevStatus));
> - return EFI_DEVICE_ERROR;
> - }
>
> Status = SdMmcHcSetBusWidth (PciIo, Slot, BusWidth);
>
> return Status;
> }
>
> +/**
> + Checks if given clock frequency is supported on
> + given bus timing.
> +
> + @param[in] ClockFreq Clock frequency to check in KHz.
> + @param[in] BusTiming Bus timing against which frequency will be
> compared.
> +
> + @retval TRUE Frequency is valid for given bus timing.
> + @retval FALSE Frequency is invalid for given bus timing.
> +**/
> +BOOLEAN
> +EmmcIsFrequencySupportedOnBusTiming (
> + IN UINT64 ClockFreq,
> + IN SD_MMC_BUS_MODE BusTiming
> + )
> +{
> + UINT32 MaxFreq;
> +
> + switch (BusTiming) {
> + case SdMmcMmcLegacy:
> + MaxFreq = 26000;
> + break;
> + case SdMmcMmcHsSdr:
> + case SdMmcMmcHsDdr:
> + MaxFreq = 52000;
> + break;
> + case SdMmcMmcHs200:
> + case SdMmcMmcHs400:
> + MaxFreq = 200000;
> + break;
> + default:
> + return FALSE;
> + }
> +
> + return (ClockFreq <= MaxFreq);
> +}
> +
> /**
> Switch the bus timing and clock frequency.
>
> @@ -669,9 +732,9 @@ EmmcSwitchBusTiming (
> UINT8 Index;
> UINT8 Value;
> UINT8 CmdSet;
> - UINT32 DevStatus;
> SD_MMC_HC_PRIVATE_DATA *Private;
> UINT8 HostCtrl1;
> + BOOLEAN DelaySendStatus;
>
> Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> //
> @@ -695,7 +758,7 @@ EmmcSwitchBusTiming (
> Value = 0;
> break;
> default:
> - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported
> BusTiming(%d\n)", BusTiming));
> + DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported
> BusTiming(%d)\n", BusTiming));
> return EFI_INVALID_PARAMETER;
> }
>
> @@ -724,6 +787,27 @@ EmmcSwitchBusTiming (
> return Status;
> }
>
> + //
> + // For cases when we switch bus timing to higher mode from current we
> want to
> + // send SEND_STATUS at current, lower, frequency then the target
> frequency to avoid
> + // stability issues. It has been observed that some designs are unable to
> process the
> + // SEND_STATUS at higher frequency during switch to HS200 @200MHz
> irrespective of the number of retries
> + // and only running the clock tuning is able to make them work on target
> frequency.
> + //
> + // For cases when we are downgrading the frequency and current high
> frequency is invalid
> + // we have to first change the frequency to target frequency and then send
> the SEND_STATUS.
> + //
> + if (EmmcIsFrequencySupportedOnBusTiming (Private-
> >Slot[Slot].CurrentFreq, BusTiming) &&
One question here. I am not sure if we need to perform the above frequency
check by EmmcIsFrequencySupportedOnBusTiming().
My understanding is that the below functions call sequence:
EmmcSetBusMode() -> EmmcGetTargetBusMode() -> EmmcGetTargetClockFreq()
can ensure target frequency specified by 'ClockFreq' is supported by the target
bus mode specified by 'BusTiming'. If current working frequency is smaller than
the target frequency, it should be supported by the target bus mode as well.
Best Regards,
Hao Wu
> + (Private->Slot[Slot].CurrentFreq < (ClockFreq * 1000))) {
> + Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + DelaySendStatus = FALSE;
> + } else {
> + DelaySendStatus = TRUE;
> + }
> +
> //
> // Convert the clock freq unit from MHz to KHz.
> //
> @@ -732,17 +816,11 @@ EmmcSwitchBusTiming (
> return Status;
> }
>
> - Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
> - if (EFI_ERROR (Status)) {
> - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Send status fails
> with %r\n", Status));
> - return Status;
> - }
> - //
> - // Check the switch operation is really successful or not.
> - //
> - if ((DevStatus & BIT7) != 0) {
> - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: The switch operation
> fails as DevStatus is 0x%08x\n", DevStatus));
> - return EFI_DEVICE_ERROR;
> + if (DelaySendStatus) {
> + Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> }
>
> return Status;
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> index b18ff3e972..57f4cf329a 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> @@ -28,7 +28,7 @@ EFI_DRIVER_BINDING_PROTOCOL
> gSdMmcPciHcDriverBinding = {
> NULL
> };
>
> -#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, \
> +#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, 0, \
> {EDKII_SD_MMC_BUS_WIDTH_IGNORE,\
> EDKII_SD_MMC_CLOCK_FREQ_IGNORE,\
> {EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE}}}
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> index 5bc3577ba2..bb3d38482f 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> @@ -83,6 +83,7 @@ typedef struct {
> BOOLEAN MediaPresent;
> BOOLEAN Initialized;
> SD_MMC_CARD_TYPE CardType;
> + UINT64 CurrentFreq;
> EDKII_SD_MMC_OPERATING_PARAMETERS OperatingParameters;
> } SD_MMC_HC_SLOT;
>
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> index 43626fff48..7971196a25 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> @@ -931,6 +931,8 @@ SdMmcHcClockSupply (
> }
> }
>
> + Private->Slot[Slot].CurrentFreq = ClockFreq;
> +
> return Status;
> }
>
> --
> 2.14.1.windows.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency
2020-02-24 7:00 ` Wu, Hao A
@ 2020-02-24 10:10 ` Albecki, Mateusz
0 siblings, 0 replies; 4+ messages in thread
From: Albecki, Mateusz @ 2020-02-24 10:10 UTC (permalink / raw)
To: Wu, Hao A, devel@edk2.groups.io; +Cc: Marcin Wojtas, Gao, Zhichao, Gao, Liming
Hi,
Yes I am fine with this change being pushed after the stable tag.
Regarding the review comments - I will remove the EmmcIsFrequencySupportedOnBusTiming. When I first implemented it I thought that frequencies <26MHz are not supported on HS200/HS400 for some reason and I forgot to remove the extra check after I have found out that is not the case.
Thanks,
Mateusz
> -----Original Message-----
> From: Wu, Hao A <hao.a.wu@intel.com>
> Sent: Monday, February 24, 2020 8:01 AM
> To: Albecki, Mateusz <mateusz.albecki@intel.com>; devel@edk2.groups.io
> Cc: Marcin Wojtas <mw@semihalf.com>; Gao, Zhichao
> <zhichao.gao@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: RE: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send
> SEND_STATUS at lower frequency
>
> > -----Original Message-----
> > From: Albecki, Mateusz
> > Sent: Friday, February 21, 2020 11:17 PM
> > To: devel@edk2.groups.io
> > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas; Gao, Zhichao; Gao,
> > Liming
> > Subject: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send
> SEND_STATUS at
> > lower frequency
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140
> >
> > To avoid stability issues on some designs the driver will now send
> > SEND_STATUS at previous, lower, frequency when upgrading the bus
> > timing.
>
>
> Hello Mateusz,
>
> The patch looks like a refinement. So I plan to push it (after the reviewing
> process) after the upcoming stable tag. Does it work for you?
>
> A couple of inline comments below:
>
>
> >
> > Cc: Hao A Wu <hao.a.wu@intel.com>
> > Cc: Marcin Wojtas <mw@semihalf.com>
> > Cc: Zhichao Gao <zhichao.gao@intel.com>
> > Cc: Liming Gao <liming.gao@intel.com>
> >
> > Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com>
> > ---
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 124
> > +++++++++++++++++----
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 2 +-
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 1 +
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 2 +
> > 4 files changed, 105 insertions(+), 24 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > index 776c0e796c..c2ebd37623 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > @@ -558,6 +558,41 @@ EmmcTuningClkForHs200 (
> > return EFI_DEVICE_ERROR;
> > }
> >
> > +/**
> > + Check the SWITCH operation status.
> > +
> > + @param[in] PassThru A pointer to the
> > EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
>
>
> Please help to add the comments for parameters 'Slot' and 'Rca'.
>
>
> > +
> > + @retval EFI_SUCCESS The SWITCH finished siccessfully.
> > + @retval others The SWITCH failed.
> > +**/
> > +EFI_STATUS
> > +EmmcCheckSwitchStatus (
> > + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
> > + IN UINT8 Slot,
> > + IN UINT16 Rca
> > + )
> > +{
> > + EFI_STATUS Status;
> > + UINT32 DevStatus;
> > +
> > + Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus); if
> > + (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: Send status fails
> > with %r\n", Status));
> > + return Status;
> > + }
> > +
> > + //
> > + // Check the switch operation is really successful or not.
> > + //
> > + if ((DevStatus & BIT7) != 0) {
> > + DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: The switch
> > operation fails as DevStatus is 0x%08x\n", DevStatus));
> > + return EFI_DEVICE_ERROR;
> > + }
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > /**
> > Switch the bus width to specified width.
> >
> > @@ -591,7 +626,6 @@ EmmcSwitchBusWidth (
> > UINT8 Index;
> > UINT8 Value;
> > UINT8 CmdSet;
> > - UINT32 DevStatus;
> >
> > //
> > // Write Byte, the Value field is written into the byte pointed by Index.
> > @@ -617,24 +651,53 @@ EmmcSwitchBusWidth (
> > return Status;
> > }
> >
> > - Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
> > + Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);
> > if (EFI_ERROR (Status)) {
> > - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Send status fails
> > with %r\n", Status));
> > return Status;
> > }
> > - //
> > - // Check the switch operation is really successful or not.
> > - //
> > - if ((DevStatus & BIT7) != 0) {
> > - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: The switch operation
> > fails as DevStatus is 0x%08x\n", DevStatus));
> > - return EFI_DEVICE_ERROR;
> > - }
> >
> > Status = SdMmcHcSetBusWidth (PciIo, Slot, BusWidth);
> >
> > return Status;
> > }
> >
> > +/**
> > + Checks if given clock frequency is supported on
> > + given bus timing.
> > +
> > + @param[in] ClockFreq Clock frequency to check in KHz.
> > + @param[in] BusTiming Bus timing against which frequency will be
> > compared.
> > +
> > + @retval TRUE Frequency is valid for given bus timing.
> > + @retval FALSE Frequency is invalid for given bus timing.
> > +**/
> > +BOOLEAN
> > +EmmcIsFrequencySupportedOnBusTiming (
> > + IN UINT64 ClockFreq,
> > + IN SD_MMC_BUS_MODE BusTiming
> > + )
> > +{
> > + UINT32 MaxFreq;
> > +
> > + switch (BusTiming) {
> > + case SdMmcMmcLegacy:
> > + MaxFreq = 26000;
> > + break;
> > + case SdMmcMmcHsSdr:
> > + case SdMmcMmcHsDdr:
> > + MaxFreq = 52000;
> > + break;
> > + case SdMmcMmcHs200:
> > + case SdMmcMmcHs400:
> > + MaxFreq = 200000;
> > + break;
> > + default:
> > + return FALSE;
> > + }
> > +
> > + return (ClockFreq <= MaxFreq);
> > +}
> > +
> > /**
> > Switch the bus timing and clock frequency.
> >
> > @@ -669,9 +732,9 @@ EmmcSwitchBusTiming (
> > UINT8 Index;
> > UINT8 Value;
> > UINT8 CmdSet;
> > - UINT32 DevStatus;
> > SD_MMC_HC_PRIVATE_DATA *Private;
> > UINT8 HostCtrl1;
> > + BOOLEAN DelaySendStatus;
> >
> > Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> > //
> > @@ -695,7 +758,7 @@ EmmcSwitchBusTiming (
> > Value = 0;
> > break;
> > default:
> > - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported
> > BusTiming(%d\n)", BusTiming));
> > + DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported
> > BusTiming(%d)\n", BusTiming));
> > return EFI_INVALID_PARAMETER;
> > }
> >
> > @@ -724,6 +787,27 @@ EmmcSwitchBusTiming (
> > return Status;
> > }
> >
> > + //
> > + // For cases when we switch bus timing to higher mode from current
> > + we
> > want to
> > + // send SEND_STATUS at current, lower, frequency then the target
> > frequency to avoid
> > + // stability issues. It has been observed that some designs are
> > + unable to
> > process the
> > + // SEND_STATUS at higher frequency during switch to HS200 @200MHz
> > irrespective of the number of retries
> > + // and only running the clock tuning is able to make them work on
> > + target
> > frequency.
> > + //
> > + // For cases when we are downgrading the frequency and current high
> > frequency is invalid
> > + // we have to first change the frequency to target frequency and
> > + then send
> > the SEND_STATUS.
> > + //
> > + if (EmmcIsFrequencySupportedOnBusTiming (Private-
> > >Slot[Slot].CurrentFreq, BusTiming) &&
>
>
> One question here. I am not sure if we need to perform the above
> frequency check by EmmcIsFrequencySupportedOnBusTiming().
>
> My understanding is that the below functions call sequence:
> EmmcSetBusMode() -> EmmcGetTargetBusMode() ->
> EmmcGetTargetClockFreq()
>
> can ensure target frequency specified by 'ClockFreq' is supported by the
> target bus mode specified by 'BusTiming'. If current working frequency is
> smaller than the target frequency, it should be supported by the target bus
> mode as well.
>
> Best Regards,
> Hao Wu
>
>
> > + (Private->Slot[Slot].CurrentFreq < (ClockFreq * 1000))) {
> > + Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > + DelaySendStatus = FALSE;
> > + } else {
> > + DelaySendStatus = TRUE;
> > + }
> > +
> > //
> > // Convert the clock freq unit from MHz to KHz.
> > //
> > @@ -732,17 +816,11 @@ EmmcSwitchBusTiming (
> > return Status;
> > }
> >
> > - Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
> > - if (EFI_ERROR (Status)) {
> > - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Send status fails
> > with %r\n", Status));
> > - return Status;
> > - }
> > - //
> > - // Check the switch operation is really successful or not.
> > - //
> > - if ((DevStatus & BIT7) != 0) {
> > - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: The switch operation
> > fails as DevStatus is 0x%08x\n", DevStatus));
> > - return EFI_DEVICE_ERROR;
> > + if (DelaySendStatus) {
> > + Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > }
> >
> > return Status;
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> > index b18ff3e972..57f4cf329a 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> > @@ -28,7 +28,7 @@ EFI_DRIVER_BINDING_PROTOCOL
> gSdMmcPciHcDriverBinding
> > = {
> > NULL
> > };
> >
> > -#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, \
> > +#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, 0, \
> > {EDKII_SD_MMC_BUS_WIDTH_IGNORE,\
> > EDKII_SD_MMC_CLOCK_FREQ_IGNORE,\
> >
> > {EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE}}}
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > index 5bc3577ba2..bb3d38482f 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > @@ -83,6 +83,7 @@ typedef struct {
> > BOOLEAN MediaPresent;
> > BOOLEAN Initialized;
> > SD_MMC_CARD_TYPE CardType;
> > + UINT64 CurrentFreq;
> > EDKII_SD_MMC_OPERATING_PARAMETERS OperatingParameters; }
> > SD_MMC_HC_SLOT;
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > index 43626fff48..7971196a25 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > @@ -931,6 +931,8 @@ SdMmcHcClockSupply (
> > }
> > }
> >
> > + Private->Slot[Slot].CurrentFreq = ClockFreq;
> > +
> > return Status;
> > }
> >
> > --
> > 2.14.1.windows.1
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-02-24 10:11 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2020-02-21 15:17 [PATCH 0/1] MdeModulePkg/SdMmcPciHcDxe: Increase driver reliability Albecki, Mateusz
2020-02-21 15:17 ` [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency Albecki, Mateusz
2020-02-24 7:00 ` Wu, Hao A
2020-02-24 10:10 ` Albecki, Mateusz
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