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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi, Yes, the new behavior should be more aligned with the SD host controller s= pec. I have been referring to section 3.7.1.2 The sequence to finalize a co= mmand which recommends to clear the interrupt in step 2 and then get the re= sponse data in step 3. Thanks, Mateusz > -----Original Message----- > From: Wu, Hao A > Sent: Wednesday, February 5, 2020 4:16 AM > To: devel@edk2.groups.io; Albecki, Mateusz > Cc: Marcin Wojtas ; Gao, Zhichao > ; Gao, Liming > Subject: RE: [edk2-devel] [PATCH 2/4] MdeModulePkg/SdMmcPciHcDxe: > Read response on command completion >=20 > One question below: >=20 >=20 > > -----Original Message----- > > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > > Albecki, Mateusz > > Sent: Monday, February 03, 2020 10:19 PM > > To: devel@edk2.groups.io > > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas; Gao, Zhichao; Gao, > > Liming > > Subject: [edk2-devel] [PATCH 2/4] MdeModulePkg/SdMmcPciHcDxe: Read > > response on command completion > > > > SdMmcPciHcDxe driver used to read response only after command and > data > > transfer completed. According to SDHCI specification response data is > > ready after the command complete status is set by the host controller. > > Getting the response data early will help debugging the cases when > > command completed but data transfer timed out. > > > > Cc: Hao A Wu > > Cc: Marcin Wojtas > > Cc: Zhichao Gao > > Cc: Liming Gao > > > > Signed-off-by: Mateusz Albecki > > --- > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 1 + > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 201 > > +++++++++++++++------ > > 2 files changed, 144 insertions(+), 58 deletions(-) > > > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > > index 5bc3577ba2..15b7d12596 100644 > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > > @@ -153,6 +153,7 @@ typedef struct { > > > > EFI_EVENT Event; > > BOOLEAN Started; > > + BOOLEAN CommandComplete; > > UINT64 Timeout; > > UINT32 Retries; > > > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > index 959645bf26..3dfaae8542 100644 > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > @@ -1708,6 +1708,7 @@ SdMmcPrintTrb ( > > DEBUG ((DebugLevel, "AdmaLengthMode: %d\n", Trb- > >AdmaLengthMode)); > > DEBUG ((DebugLevel, "Event: %d\n", Trb->Event)); > > DEBUG ((DebugLevel, "Started: %d\n", Trb->Started)); > > + DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb- > > >CommandComplete)); > > DEBUG ((DebugLevel, "Timeout: %d\n", Trb->Timeout)); > > DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries)); > > DEBUG ((DebugLevel, "Adma32Desc: %X\n", Trb->Adma32Desc)); @@ > > -1758,6 +1759,7 @@ SdMmcCreateTrb ( > > Trb->Packet =3D Packet; > > Trb->Event =3D Event; > > Trb->Started =3D FALSE; > > + Trb->CommandComplete =3D FALSE; > > Trb->Timeout =3D Packet->Timeout; > > Trb->Retries =3D SD_MMC_TRB_RETRIES; > > Trb->Private =3D Private; > > @@ -2352,6 +2354,99 @@ SdMmcCheckAndRecoverErrors ( > > return ErrorStatus; > > } > > > > +/** > > + Reads the response data into the TRB buffer. > > + This function assumes that caller made sure that > > + command has completed. > > + > > + @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA > > instance. > > + @param[in] Trb The pointer to the SD_MMC_HC_TRB instance. > > + > > + @retval EFI_SUCCESS Response read successfully. > > + @retval Others Failed to get response. > > +**/ > > +EFI_STATUS > > +SdMmcGetResponse ( > > + IN SD_MMC_HC_PRIVATE_DATA *Private, > > + IN SD_MMC_HC_TRB *Trb > > + ) > > +{ > > + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; > > + UINT8 Index; > > + UINT32 Response[4]; > > + EFI_STATUS Status; > > + > > + Packet =3D Trb->Packet; > > + > > + if (Packet->SdMmcCmdBlk->CommandType =3D=3D > SdMmcCommandTypeBc) { > > + return EFI_SUCCESS; > > + } > > + > > + for (Index =3D 0; Index < 4; Index++) { > > + Status =3D SdMmcHcRwMmio ( > > + Private->PciIo, > > + Trb->Slot, > > + SD_MMC_HC_RESPONSE + Index * 4, > > + TRUE, > > + sizeof (UINT32), > > + &Response[Index] > > + ); > > + if (EFI_ERROR (Status)) { > > + return Status; > > + } > > + } > > + CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response)); > > + > > + return EFI_SUCCESS; > > +} > > + > > +/** > > + Checks if the command completed. If the command > > + completed it gets the response and records the > > + command completion in the TRB. > > + > > + @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA > > instance. > > + @param[in] Trb The pointer to the SD_MMC_HC_TRB instance. > > + @param[in] IntStatus Snapshot of the normal interrupt status regis= ter. > > + > > + @retval EFI_SUCCESS Command completed successfully. > > + @retval EFI_NOT_READY Command completion still pending. > > + @retval Others Command failed to complete. > > +**/ > > +EFI_STATUS > > +SdMmcCheckCommandComplete ( > > + IN SD_MMC_HC_PRIVATE_DATA *Private, > > + IN SD_MMC_HC_TRB *Trb, > > + IN UINT16 IntStatus > > + ) > > +{ > > + UINT16 Data16; > > + EFI_STATUS Status; > > + > > + if ((IntStatus & BIT0) !=3D 0) { > > + Data16 =3D BIT0; > > + Status =3D SdMmcHcRwMmio ( > > + Private->PciIo, > > + Trb->Slot, > > + SD_MMC_HC_NOR_INT_STS, > > + FALSE, > > + sizeof (Data16), > > + &Data16 > > + ); >=20 >=20 > Previously, the driver cleans the Command Complete (BIT0) at the beginni= ng > of the execution of the next TRB in function SdMmcExecTrb(). Now, the > patch will clean this bit just after checking it. >=20 > So the behavior in the patch is more aligned with the SD Host Controller= Spec, > right? >=20 > Best Regards, > Hao Wu >=20 >=20 > > + if (EFI_ERROR (Status)) { > > + return Status; > > + } > > + Status =3D SdMmcGetResponse (Private, Trb); > > + if (EFI_ERROR (Status)) { > > + return Status; > > + } > > + Trb->CommandComplete =3D TRUE; > > + return EFI_SUCCESS; > > + } > > + > > + return EFI_NOT_READY; > > +} > > + > > /** > > Check the TRB execution result. > > > > @@ -2372,9 +2467,7 @@ SdMmcCheckTrbResult ( > > EFI_STATUS Status; > > EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; > > UINT16 IntStatus; > > - UINT32 Response[4]; > > UINT64 SdmaAddr; > > - UINT8 Index; > > UINT32 PioLength; > > > > Packet =3D Trb->Packet; > > @@ -2402,6 +2495,54 @@ SdMmcCheckTrbResult ( > > goto Done; > > } > > > > + // > > + // Tuning commands are the only ones that do not generate command > > + // complete interrupt. Process them here before entering the code > > + // that waits for command completion. > > + // > > + if (((Private->Slot[Trb->Slot].CardType =3D=3D EmmcCardType) && > > + (Packet->SdMmcCmdBlk->CommandIndex =3D=3D > > EMMC_SEND_TUNING_BLOCK)) || > > + ((Private->Slot[Trb->Slot].CardType =3D=3D SdCardType) && > > + (Packet->SdMmcCmdBlk->CommandIndex =3D=3D > > SD_SEND_TUNING_BLOCK))) { > > + // > > + // When performing tuning procedure (Execute Tuning is set to 1) > > + through > > PIO mode, > > + // wait Buffer Read Ready bit of Normal Interrupt Status Register= to be 1. > > + // Refer to SD Host Controller Simplified Specification 3.0 > > + figure 2-29 for > > details. > > + // > > + if ((IntStatus & BIT5) =3D=3D BIT5) { > > + // > > + // Clear Buffer Read Ready interrupt at first. > > + // > > + IntStatus =3D BIT5; > > + SdMmcHcRwMmio (Private->PciIo, Trb->Slot, > > SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus); > > + // > > + // Read data out from Buffer Port register > > + // > > + for (PioLength =3D 0; PioLength < Trb->DataLen; PioLength +=3D = 4) { > > + SdMmcHcRwMmio (Private->PciIo, Trb->Slot, > > SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength); > > + } > > + Status =3D EFI_SUCCESS; > > + goto Done; > > + } > > + } > > + > > + if (!Trb->CommandComplete) { > > + Status =3D SdMmcCheckCommandComplete (Private, Trb, IntStatus); > > + if (EFI_ERROR (Status)) { > > + goto Done; > > + } else { > > + // > > + // If the command doesn't require data transfer skip the transf= er > > + // complete checking. > > + // > > + if ((Packet->SdMmcCmdBlk->CommandType !=3D > > SdMmcCommandTypeAdtc) && > > + (Packet->SdMmcCmdBlk->ResponseType !=3D > SdMmcResponseTypeR1b) > > && > > + (Packet->SdMmcCmdBlk->ResponseType !=3D > > + SdMmcResponseTypeR5b)) > > { > > + goto Done; > > + } > > + } > > + } > > + > > // > > // Check Transfer Complete bit is set or not. > > // > > @@ -2459,65 +2600,9 @@ SdMmcCheckTrbResult ( > > Trb->DataPhy =3D (UINT64)(UINTN)SdmaAddr; > > } > > > > - if ((Packet->SdMmcCmdBlk->CommandType !=3D > SdMmcCommandTypeAdtc) && > > - (Packet->SdMmcCmdBlk->ResponseType !=3D > SdMmcResponseTypeR1b) > > && > > - (Packet->SdMmcCmdBlk->ResponseType !=3D > SdMmcResponseTypeR5b)) { > > - if ((IntStatus & BIT0) =3D=3D BIT0) { > > - Status =3D EFI_SUCCESS; > > - goto Done; > > - } > > - } > > - > > - if (((Private->Slot[Trb->Slot].CardType =3D=3D EmmcCardType) && > > - (Packet->SdMmcCmdBlk->CommandIndex =3D=3D > > EMMC_SEND_TUNING_BLOCK)) || > > - ((Private->Slot[Trb->Slot].CardType =3D=3D SdCardType) && > > - (Packet->SdMmcCmdBlk->CommandIndex =3D=3D > > SD_SEND_TUNING_BLOCK))) { > > - // > > - // When performing tuning procedure (Execute Tuning is set to 1) > through > > PIO mode, > > - // wait Buffer Read Ready bit of Normal Interrupt Status Register= to be 1. > > - // Refer to SD Host Controller Simplified Specification 3.0 figur= e 2-29 for > > details. > > - // > > - if ((IntStatus & BIT5) =3D=3D BIT5) { > > - // > > - // Clear Buffer Read Ready interrupt at first. > > - // > > - IntStatus =3D BIT5; > > - SdMmcHcRwMmio (Private->PciIo, Trb->Slot, > > SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus); > > - // > > - // Read data out from Buffer Port register > > - // > > - for (PioLength =3D 0; PioLength < Trb->DataLen; PioLength +=3D = 4) { > > - SdMmcHcRwMmio (Private->PciIo, Trb->Slot, > > SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength); > > - } > > - Status =3D EFI_SUCCESS; > > - goto Done; > > - } > > - } > > > > Status =3D EFI_NOT_READY; > > Done: > > - // > > - // Get response data when the cmd is executed successfully. > > - // > > - if (!EFI_ERROR (Status)) { > > - if (Packet->SdMmcCmdBlk->CommandType !=3D > SdMmcCommandTypeBc) { > > - for (Index =3D 0; Index < 4; Index++) { > > - Status =3D SdMmcHcRwMmio ( > > - Private->PciIo, > > - Trb->Slot, > > - SD_MMC_HC_RESPONSE + Index * 4, > > - TRUE, > > - sizeof (UINT32), > > - &Response[Index] > > - ); > > - if (EFI_ERROR (Status)) { > > - SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE); > > - return Status; > > - } > > - } > > - CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response)); > > - } > > - } > > > > if (Status !=3D EFI_NOT_READY) { > > SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE); > > -- > > 2.14.1.windows.1 > > > > -------------------------------------------------------------------- > > > > Intel Technology Poland sp. z o.o. > > ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII > > Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP > > 957- > > 07-52-316 | Kapital zakladowy 200.000 PLN. > > > > Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego > > adresata i moze zawierac informacje poufne. W razie przypadkowego > > otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale > > jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest > > zabronione. > > This e-mail and any attachments may contain confidential material for > > the sole use of the intended recipient(s). If you are not the intended > > recipient, please contact the sender and delete all copies; any review > > or distribution by others is strictly prohibited. > > > > > >=20 >=20 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wyd= zial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-3= 16 | Kapital zakladowy 200.000 PLN. Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresat= a i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej w= iadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakie= kolwiek przegladanie lub rozpowszechnianie jest zabronione. This e-mail and any attachments may contain confidential material for the = sole use of the intended recipient(s). If you are not the intended recipien= t, please contact the sender and delete all copies; any review or distribut= ion by others is strictly prohibited.