Does anyone know the definition of EFI_SYSTEM_CONTEXT_X64.Gdtr[2] and EFI_SYSTEM_CONTEXT_X64.Idtr[2]

Does anyone know the definition of EFI_SYSTEM_CONTEXT_X64.Gdtr[2] and EFI_SYSTEM_CONTEXT_X64.Idtr[2]

[Andrew Fish]

The x86 instructions do limit then base, but the code is storing base, then limit. Does anyone remember if this is properly defined some place?

Thanks,

Andrew Fish

Re: [edk2-devel] Does anyone know the definition of EFI_SYSTEM_CONTEXT_X64.Gdtr[2] and EFI_SYSTEM_CONTEXT_X64.Idtr[2]

[Michael D Kinney]

Hi Andrew,

Are you referring to the order the fields are filled in by the C code
before the x86 instruction is executed?  I do not think that matters.  

Thanks,

Mike

> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On
> Behalf Of Andrew Fish via groups.io
> Sent: Wednesday, June 3, 2020 4:39 PM
> To: edk2-devel-groups-io <devel@edk2.groups.io>
> Subject: [edk2-devel] Does anyone know the definition of
> EFI_SYSTEM_CONTEXT_X64.Gdtr[2] and
> EFI_SYSTEM_CONTEXT_X64.Idtr[2]
> 
> The x86 instructions do limit then base, but the code is
> storing base, then limit. Does anyone remember if this
> is properly defined some place?
> 
> Thanks,
> 
> Andrew Fish
> 

Re: [edk2-devel] Does anyone know the definition of EFI_SYSTEM_CONTEXT_X64.Gdtr[2] and EFI_SYSTEM_CONTEXT_X64.Idtr[2]

[Andrew Fish]

> On Jun 3, 2020, at 5:37 PM, Michael D Kinney <michael.d.kinney@intel.com> wrote:
> 
> Hi Andrew,
> 
> Are you referring to the order the fields are filled in by the C code
> before the x86 instruction is executed?  I do not think that matters.
> 

Mike,

The instructions point to a blob of data that is not UINTN aligned. These register point to a limit then base address. If you execute the instruction you get 2 bytes of limit and 4 or 8 bytes of data. But Idtr[0] is base and Intro[1] is limit, so reversed from the instruction order. What defines index 0 vs. index 1 data contents?

Thanks,

Andrew Fish

> Thanks,
> 
> Mike
> 
>> -----Original Message-----
>> From: devel@edk2.groups.io <devel@edk2.groups.io> On
>> Behalf Of Andrew Fish via groups.io
>> Sent: Wednesday, June 3, 2020 4:39 PM
>> To: edk2-devel-groups-io <devel@edk2.groups.io>
>> Subject: [edk2-devel] Does anyone know the definition of
>> EFI_SYSTEM_CONTEXT_X64.Gdtr[2] and
>> EFI_SYSTEM_CONTEXT_X64.Idtr[2]
>> 
>> The x86 instructions do limit then base, but the code is
>> storing base, then limit. Does anyone remember if this
>> is properly defined some place?
>> 
>> Thanks,
>> 
>> Andrew Fish
>> 
> 
> 
> 
> 

Re: [edk2-devel] Does anyone know the definition of EFI_SYSTEM_CONTEXT_X64.Gdtr[2] and EFI_SYSTEM_CONTEXT_X64.Idtr[2]

[Michael D Kinney]

Hi Andrew,

I see the following assembly that reads GDTR and IDTR from
CPU and saves them into the context structure:

;; UINT32  Gdtr[2], Idtr[2];
    sub     esp, 8
    sidt    [esp]
    mov     eax, [esp + 2]
    xchg    eax, [esp]
    and     eax, 0xFFFF
    mov     [esp+4], eax

    sub     esp, 8
    sgdt    [esp]
    mov     eax, [esp + 2]
    xchg    eax, [esp]
    and     eax, 0xFFFF
    mov     [esp+4], eax

This data structure is defined in UEFI Spec, but I do not
see a detailed description of these 2 arrays and the meaning
of each entry.  Seems like a gap in the spec description.

Mike

> -----Original Message-----
> From: Andrew Fish <afish@apple.com>
> Sent: Wednesday, June 3, 2020 5:57 PM
> To: edk2-devel-groups-io <devel@edk2.groups.io>; Kinney,
> Michael D <michael.d.kinney@intel.com>
> Subject: Re: [edk2-devel] Does anyone know the
> definition of EFI_SYSTEM_CONTEXT_X64.Gdtr[2] and
> EFI_SYSTEM_CONTEXT_X64.Idtr[2]
> 
> 
> 
> > On Jun 3, 2020, at 5:37 PM, Michael D Kinney
> <michael.d.kinney@intel.com> wrote:
> >
> > Hi Andrew,
> >
> > Are you referring to the order the fields are filled
> in by the C code
> > before the x86 instruction is executed?  I do not
> think that matters.
> >
> 
> Mike,
> 
> The instructions point to a blob of data that is not
> UINTN aligned. These register point to a limit then base
> address. If you execute the instruction you get 2 bytes
> of limit and 4 or 8 bytes of data. But Idtr[0] is base
> and Intro[1] is limit, so reversed from the instruction
> order. What defines index 0 vs. index 1 data contents?
> 
> Thanks,
> 
> Andrew Fish
> 
> > Thanks,
> >
> > Mike
> >
> >> -----Original Message-----
> >> From: devel@edk2.groups.io <devel@edk2.groups.io> On
> >> Behalf Of Andrew Fish via groups.io
> >> Sent: Wednesday, June 3, 2020 4:39 PM
> >> To: edk2-devel-groups-io <devel@edk2.groups.io>
> >> Subject: [edk2-devel] Does anyone know the definition
> of
> >> EFI_SYSTEM_CONTEXT_X64.Gdtr[2] and
> >> EFI_SYSTEM_CONTEXT_X64.Idtr[2]
> >>
> >> The x86 instructions do limit then base, but the code
> is
> >> storing base, then limit. Does anyone remember if
> this
> >> is properly defined some place?
> >>
> >> Thanks,
> >>
> >> Andrew Fish
> >>
> >
> >
> > 
> >

Re: [edk2-devel] Does anyone know the definition of EFI_SYSTEM_CONTEXT_X64.Gdtr[2] and EFI_SYSTEM_CONTEXT_X64.Idtr[2]

[Andrew Fish]

> On Jun 3, 2020, at 6:43 PM, Kinney, Michael D <michael.d.kinney@intel.com> wrote:
> 
> Hi Andrew,
> 
> I see the following assembly that reads GDTR and IDTR from
> CPU and saves them into the context structure:
> 
> ;; UINT32  Gdtr[2], Idtr[2];
>    sub     esp, 8
>    sidt    [esp]
>    mov     eax, [esp + 2]
>    xchg    eax, [esp]
>    and     eax, 0xFFFF
>    mov     [esp+4], eax
> 
>    sub     esp, 8
>    sgdt    [esp]
>    mov     eax, [esp + 2]
>    xchg    eax, [esp]
>    and     eax, 0xFFFF
>    mov     [esp+4], eax
> 
> This data structure is defined in UEFI Spec, but I do not
> see a detailed description of these 2 arrays and the meaning
> of each entry.  Seems like a gap in the spec description.
> 

Mike,

Yea that is what I saw too, but I had code code doing the opposite and passing the context over did not go well. I can think of at least 3 ways ti could be mapped? Match the instruction, Base 1st, Limit 1st. 

Thanks,

Andrew Fish

> Mike
> 
>> -----Original Message-----
>> From: Andrew Fish <afish@apple.com>
>> Sent: Wednesday, June 3, 2020 5:57 PM
>> To: edk2-devel-groups-io <devel@edk2.groups.io>; Kinney,
>> Michael D <michael.d.kinney@intel.com>
>> Subject: Re: [edk2-devel] Does anyone know the
>> definition of EFI_SYSTEM_CONTEXT_X64.Gdtr[2] and
>> EFI_SYSTEM_CONTEXT_X64.Idtr[2]
>> 
>> 
>> 
>>> On Jun 3, 2020, at 5:37 PM, Michael D Kinney
>> <michael.d.kinney@intel.com> wrote:
>>> 
>>> Hi Andrew,
>>> 
>>> Are you referring to the order the fields are filled
>> in by the C code
>>> before the x86 instruction is executed?  I do not
>> think that matters.
>>> 
>> 
>> Mike,
>> 
>> The instructions point to a blob of data that is not
>> UINTN aligned. These register point to a limit then base
>> address. If you execute the instruction you get 2 bytes
>> of limit and 4 or 8 bytes of data. But Idtr[0] is base
>> and Intro[1] is limit, so reversed from the instruction
>> order. What defines index 0 vs. index 1 data contents?
>> 
>> Thanks,
>> 
>> Andrew Fish
>> 
>>> Thanks,
>>> 
>>> Mike
>>> 
>>>> -----Original Message-----
>>>> From: devel@edk2.groups.io <devel@edk2.groups.io> On
>>>> Behalf Of Andrew Fish via groups.io
>>>> Sent: Wednesday, June 3, 2020 4:39 PM
>>>> To: edk2-devel-groups-io <devel@edk2.groups.io>
>>>> Subject: [edk2-devel] Does anyone know the definition
>> of
>>>> EFI_SYSTEM_CONTEXT_X64.Gdtr[2] and
>>>> EFI_SYSTEM_CONTEXT_X64.Idtr[2]
>>>> 
>>>> The x86 instructions do limit then base, but the code
>> is
>>>> storing base, then limit. Does anyone remember if
>> this
>>>> is properly defined some place?
>>>> 
>>>> Thanks,
>>>> 
>>>> Andrew Fish
>>>> 
>>> 
>>> 
>>> 
>>> 
>