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Wed, 2 Aug 2023 21:48:29 +0000 From: "Jeshua Smith via groups.io" To: "devel@edk2.groups.io" , Jeshua Smith , "sami.mujawar@arm.com" CC: "ardb+tianocore@kernel.org" , "thomas.abraham@arm.com" , "Pierre.gondois@arm.com" , "Anshuman.Khandual@arm.com" , "Matteo.Carlini@arm.com" , "Akanksha.Jain2@arm.com" , "Sibel.Allinson@arm.com" , "nd@arm.com" Subject: Re: [edk2-devel] [PATCH edk2-platforms v1 2/3] Platform/ARM: FVP: Specify TRBE interrupt in MADT GICC Thread-Topic: [edk2-devel] [PATCH edk2-platforms v1 2/3] Platform/ARM: FVP: Specify TRBE interrupt in MADT GICC Thread-Index: AQHZvuM1NXXCdqsudkGGJJ5vWaKM3q/Vnf6QgAH5AMA= Date: Wed, 2 Aug 2023 21:48:29 +0000 Message-ID: References: <20230725103105.8068-1-sami.mujawar@arm.com> <20230725103105.8068-3-sami.mujawar@arm.com> <17774C7EDBBD6733.29484@groups.io> In-Reply-To: <17774C7EDBBD6733.29484@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB3373.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2ee85837-e41a-4a51-75c4-08db93a23575 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Aug 2023 21:48:29.3398 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 7FyY+H1O5upFvkyjMpyoGAqk3hx3LkGfKIxD2R1G+AE5nVWUkx/Wmt6cfpacHRhRfJsoNGSWB9aA6rvlswPKoA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5200 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeshuas@nvidia.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: qXutULkrGMcGXdwpXZd6b30ix7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Lvj0ise7; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io This code depends on ArmReadIdAA64Dfr0(), which as far as I can tell is not= present in the EDK2 repo or the patch series mentioned in your 0/3 message= . -----Original Message----- From: devel@edk2.groups.io On Behalf Of Jeshua Smith= via groups.io Sent: Tuesday, August 1, 2023 9:38 AM To: devel@edk2.groups.io; sami.mujawar@arm.com Cc: ardb+tianocore@kernel.org; thomas.abraham@arm.com; Pierre.gondois@arm.c= om; Anshuman.Khandual@arm.com; Matteo.Carlini@arm.com; Akanksha.Jain2@arm.c= om; Sibel.Allinson@arm.com; nd@arm.com Subject: Re: [edk2-devel] [PATCH edk2-platforms v1 2/3] Platform/ARM: FVP: = Specify TRBE interrupt in MADT GICC External email: Use caution opening links or attachments This comment in the code looks wrong: + // TRBE Interrupt is PPI 13 on FVP model. + TrbeInterrupt =3D 31; -----Original Message----- From: devel@edk2.groups.io On Behalf Of Sami Mujawar= via groups.io Sent: Tuesday, July 25, 2023 4:31 AM To: devel@edk2.groups.io Cc: Sami Mujawar ; ardb+tianocore@kernel.org; thomas.= abraham@arm.com; Pierre.gondois@arm.com; Anshuman.Khandual@arm.com; Matteo.= Carlini@arm.com; Akanksha.Jain2@arm.com; Sibel.Allinson@arm.com; nd@arm.com Subject: [edk2-devel] [PATCH edk2-platforms v1 2/3] Platform/ARM: FVP: Spec= ify TRBE interrupt in MADT GICC External email: Use caution opening links or attachments When TRBE is enabled the FVP model uses the PPI 15 (i.e. INT ID 31) as the = TRBE interrupt. Ref: https://www.kernel.org/doc/Documentation/ devicetree/bindings/arm/arm,trace-buffer-extension.yaml Therefore, check the debug feature register ID_AA64DFR0_EL1.TraceBuffer fie= ld to see if TRBE is enabled and configure the TRBE interrupt in the GICC s= tructure in the MADT ACPI table. Note: To enable TRBE support in the FVP REvC model 1. Build TF-A with the C= TX_INCLUDE_AARCH32_REGS=3D0 build flag set, otherwise this results in an exception when booting TF-A. 2. Set the model parameters to enable TRBE -C cluster0.has_trbe=3D1 -C cluster1.has_trbe=3D1 Signed-off-by: Sami Mujawar --- Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/Conf= igurationManager.c | 39 ++++++++++++++++---- Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/Conf= igurationManagerDxe.inf | 3 +- 2 files changed, 33 insertions(+), 9 deletions(-) diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationMan= agerDxe/ConfigurationManager.c b/Platform/ARM/VExpressPkg/ConfigurationMana= ger/ConfigurationManagerDxe/ConfigurationManager.c index 4df2d6cdae58df344804a8b41208a3adb8ee0110..03393905be1c627b7cdbaa0efed= 33e920072c8cb 100644 --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.c +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManager +++ Dxe/ConfigurationManager.c @@ -1,7 +1,7 @@ /** @file Configuration Manager Dxe - Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.
+ Copyright (c) 2017 - 2023, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -37,8 +38,8 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInfo= =3D { { // FADT Table { - EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, + EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt), NULL }, @@ -51,8 +52,8 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInfo= =3D { }, // MADT Table { - EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, + EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt), NULL }, @@ -109,15 +110,15 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepository= Info =3D { }, // Boot architecture information - { EFI_ACPI_6_3_ARM_PSCI_COMPLIANT }, // BootArchFlags + { EFI_ACPI_6_5_ARM_PSCI_COMPLIANT }, // BootArchFlags #ifdef HEADLESS_PLATFORM // Fixed feature flag information - { EFI_ACPI_6_3_HEADLESS }, // Fixed feature flags + { EFI_ACPI_6_5_HEADLESS }, // Fixed feature flags #endif // Power management profile information - { EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement Pro= file + { EFI_ACPI_6_5_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement Pro= file /* GIC CPU Interface information GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, EnergyEfficien= cy) @@ -474,6 +475,9 @@ InitializePlatformRepository ( ) { EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINT64 DbgFeatures; + UINTN Index; + UINT16 TrbeInterrupt; PlatformRepo =3D This->PlatRepoInfo; @@ -491,6 +495,25 @@ InitializePlatformRepository ( PlatformRepo->GicCInfo[6].MPIDR =3D GET_MPID_MT (1, 2, 0); PlatformRepo->GicCInfo[7].MPIDR =3D GET_MPID_MT (1, 3, 0); } + + TrbeInterrupt =3D 0; + DbgFeatures =3D ArmReadIdAA64Dfr0 (); + DEBUG (( + DEBUG_INFO, + "Debug Feature Register 0 - ID_AA64DFR0_EL1 =3D 0x%lx\n", + DbgFeatures + )); + + // The ID_AA64DFR0_EL1.TraceBuffer field identifies support for FEAT_TRB= E. + if (((DbgFeatures >> 44) & 0xF) !=3D 0) { + // TRBE Interrupt is PPI 13 on FVP model. + TrbeInterrupt =3D 31; + } + + for (Index =3D 0; Index < PLAT_CPU_COUNT; Index++) { + PlatformRepo->GicCInfo[Index].TrbeInterrupt =3D TrbeInterrupt; } + return EFI_SUCCESS; } diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationMan= agerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/VExpressPkg/Configuratio= nManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf index b53daf51d4b1afd45e41d0debb0b9f084f135f6a..dd08f8597768d4de62941c5fd74= e329c431582b0 100644 --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManagerDxe.inf +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManager +++ Dxe/ConfigurationManagerDxe.inf @@ -1,7 +1,7 @@ ## @file # Configuration Manager Dxe # -# Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.
+# Copyright (c) 2017 - 2023, Arm Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent ## @@ -34,6 +34,7 @@ [Pac= kages] Platform/ARM/VExpressPkg/ArmVExpressPkg.dec [LibraryClasses] + ArmLib ArmPlatformLib PrintLib UefiBootServicesTableLib -- 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107478): https://edk2.groups.io/g/devel/message/107478 Mute This Topic: https://groups.io/mt/100347409/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-